ATMEGA640 datasheet(35/449 Pages) ATMEL

35 / 449 page

ATmega640/1280/1281/2560/2561

2549K–AVR–01/07

address space is configured as one sector, the wait-states are configured by the

SRW11 and SRW10 bits.

• Bit 3:2 – SRW11, SRW10: Wait-state Select Bits for Upper Sector

The SRW11 and SRW10 bits control the number of wait-states for the upper sector of

the external memory address space, see Table 8.

• Bit 1:0 – SRW01, SRW00: Wait-state Select Bits for Lower Sector

The SRW01 and SRW00 bits control the number of wait-states for the lower sector of

the external memory address space, see Table 8.

Note:

1. n = 0 or 1 (lower/upper sector).

For further details of the timing and wait-states of the External Memory Interface, see

Figures 15 through Figures 18 for how the setting of the SRW bits affects the timing.

Table 7. Sector limits with different settings of SRL2:0

SRL2

SRL1

SRL0

Sector Limits

Lower sector = N/A

Upper sector = 0x2200 - 0xFFFF

Lower sector = 0x2200 - 0x3FFF

Upper sector = 0x4000 - 0xFFFF

Lower sector = 0x2200 - 0x5FFF

Upper sector = 0x6000 - 0xFFFF

Lower sector = 0x2200 - 0x7FFF

Upper sector = 0x8000 - 0xFFFF

Lower sector = 0x2200 - 0x9FFF

Upper sector = 0xA000 - 0xFFFF

Lower sector = 0x2200 - 0xBFFF

Upper sector = 0xC000 - 0xFFFF

Lower sector = 0x2200 - 0xDFFF

Upper sector = 0xE000 - 0xFFFF

Table 8. Wait States

(1)

SRWn1

SRWn0

Wait States

No wait-states

Wait one cycle during read/write strobe

Wait two cycles during read/write strobe

Wait two cycles during read/write and wait one cycle before driving out

new address

ATMEGA640 Datasheet(PDF) 35 Page - ATMEL Corporation

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