ATMEGA640 datasheet(16/449 Pages) ATMEL

16 / 449 page

ATmega640/1280/1281/2560/2561

2549K–AVR–01/07

Instruction Execution

Timing

This section describes the general access timing concepts for instruction execution. The

AVR CPU is driven by the CPU clock clk

CPU, directly generated from the selected clock

source for the chip. No internal clock division is used.

Figure 10 shows the parallel instruction fetches and instruction executions enabled by

the Harvard architecture and the fast-access Register File concept. This is the basic

pipelining concept to obtain up to 1 MIPS per MHz with the corresponding unique results

for functions per cost, functions per clocks, and functions per power-unit.

Figure 10. The Parallel Instruction Fetches and Instruction Executions

Figure 11 shows the internal timing concept for the Register File. In a single clock cycle

an ALU operation using two register operands is executed, and the result is stored back

to the destination register.

Figure 11. Single Cycle ALU Operation

clk

1st Instruction Fetch

1st Instruction Execute

2nd Instruction Fetch

2nd Instruction Execute

3rd Instruction Fetch

3rd Instruction Execute

4th Instruction Fetch

CPU

Total Execution Time

ALU Operation Execute

Result Write Back

clk

CPU

ATMEGA640 Datasheet(PDF) 16 Page - ATMEL Corporation