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ATMEGA640 Datasheet(PDF) 54 Page - ATMEL Corporation |
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ATMEGA640 Datasheet(HTML) 54 Page - ATMEL Corporation |
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54 / 449 page ![]() 54 ATmega640/1280/1281/2560/2561 2549K–AVR–01/07 Register Description SMCR – Sleep Mode Control Register The Sleep Mode Control Register contains control bits for power management. • Bits 3, 2, 1 – SM2:0: Sleep Mode Select Bits 2, 1, and 0 These bits select between the five available sleep modes as shown in Table 25. Note: 1. Standby modes are only recommended for use with external crystals or resonators. • Bit 1 – SE: Sleep Enable The SE bit must be written to logic one to make the MCU enter the sleep mode when the SLEEP instruction is executed. To avoid the MCU entering the sleep mode unless it is the programmer’s purpose, it is recommended to write the Sleep Enable (SE) bit to one just before the execution of the SLEEP instruction and to clear it immediately after wak- ing up. Bit 7654 321 0 0x33 (0x53) –––– SM2 SM1 SM0 SE SMCR Read/Write R RRR R/W R/W R/W R/W Initial Value 0000 000 0 Table 25. Sleep Mode Select SM2 SM1 SM0 Sleep Mode 00 0 Idle 0 0 1 ADC Noise Reduction 0 1 0 Power-down 01 1 Power-save 1 0 0 Reserved 1 0 1 Reserved 1 1 0 Standby(1) 1 1 1 Extended Standby(1) |
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