ATMEGA640 datasheet(119/449 Pages) ATMEL

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119

ATmega640/1280/1281/2560/2561

2549K–AVR–01/07

8-bit Timer/Counter0

with PWM

Timer/Counter0 is a general purpose 8-bit Timer/Counter module, with two independent

Output Compare Units, and with PWM support. It allows accurate program execution

timing (event management) and wave generation. The main features are:

• Two Independent Output Compare Units

• Double Buffered Output Compare Registers

• Clear Timer on Compare Match (Auto Reload)

• Glitch Free, Phase Correct Pulse Width Modulator (PWM)

• Variable PWM Period

• Frequency Generator

• Three Independent Interrupt Sources (TOV0, OCF0A, and OCF0B)

Overview

A simplified block diagram of the 8-bit Timer/Counter is shown in Figure 37. For the

actual placement of I/O pins, refer to “TQFP-pinout ATmega640/1280/2560” on page 2.

CPU accessible I/O Registers, including I/O bits and I/O pins, are shown in bold. The

device-specific I/O Register and bit locations are listed in the “Register Description” on

page 130.

Figure 37. 8-bit Timer/Counter Block Diagram

Registers

The Timer/Counter (TCNT0) and Output Compare Registers (OCR0A and OCR0B) are

8-bit registers. Interrupt request (abbreviated to Int.Req. in the figure) signals are all vis-

ible in the Timer Interrupt Flag Register (TIFR0). All interrupts are individually masked

with the Timer Interrupt Mask Register (TIMSK0). TIFR0 and TIMSK0 are not shown in

the figure.

The Timer/Counter can be clocked internally, via the prescaler, or by an external clock

source on the T0 pin. The Clock Select logic block controls which clock source and edge

the Timer/Counter uses to increment (or decrement) its value. The Timer/Counter is

inactive when no clock source is selected. The output from the Clock Select logic is

referred to as the timer clock (clk

T0).

The double buffered Output Compare Registers (OCR0A and OCR0B) are compared

with the Timer/Counter value at all times. The result of the compare can be used by the

Waveform Generator to generate a PWM or variable frequency output on the Output

Clock Select

Timer/Counter

OCRnA

OCRnB

TCNTn

Waveform

Generation

Waveform

Generation

OCnA

OCnB

Fixed

TOP

Value

Control Logic

= 0

TOP

BOTTOM

Count

Clear

Direction

TOVn

(Int.Req.)

OCnA

(Int.Req.)

OCnB

(Int.Req.)

TCCRnA

TCCRnB

Edge

Detector

( From Prescaler )

clk

ATMEGA640 Datasheet(PDF) 119 Page - ATMEL Corporation

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