ATMEGA640 datasheet(218/449 Pages) ATMEL

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218

ATmega640/1280/1281/2560/2561

2549K–AVR–01/07

Transmitter Flags and

Interrupts

The USART Transmitter has two flags that indicate its state: USART Data Register

Empty (UDREn) and Transmit Complete (TXCn). Both flags can be used for generating

interrupts.

The Data Register Empty (UDREn) Flag indicates whether the transmit buffer is ready to

receive new data. This bit is set when the transmit buffer is empty, and cleared when the

transmit buffer contains data to be transmitted that has not yet been moved into the Shift

the UCSRnA Register.

When the Data Register Empty Interrupt Enable (UDRIEn) bit in UCSRnB is written to

one, the USART Data Register Empty Interrupt will be executed as long as UDREn is

set (provided that global interrupts are enabled). UDREn is cleared by writing UDRn.

When interrupt-driven data transmission is used, the Data Register Empty interrupt rou-

tine must either write new data to UDRn in order to clear UDREn or disable the Data

terminates.

The Transmit Complete (TXCn) Flag bit is set one when the entire frame in the Transmit

Shift Register has been shifted out and there are no new data currently present in the

transmit buffer. The TXCn Flag bit is automatically cleared when a transmit complete

interrupt is executed, or it can be cleared by writing a one to its bit location. The TXCn

Flag is useful in half-duplex communication interfaces (like the RS-485 standard), where

a transmitting application must enter receive mode and free the communication bus

immediately after completing the transmission.

When the Transmit Compete Interrupt Enable (TXCIEn) bit in UCSRnB is set, the

USART Transmit Complete Interrupt will be executed when the TXCn Flag becomes set

(provided that global interrupts are enabled). When the transmit complete interrupt is

used, the interrupt handling routine does not have to clear the TXCn Flag, this is done

automatically when the interrupt is executed.

Parity Generator

The Parity Generator calculates the parity bit for the serial frame data. When parity bit is

enabled (UPMn1 = 1), the transmitter control logic inserts the parity bit between the last

data bit and the first stop bit of the frame that is sent.

Disabling the Transmitter

The disabling of the Transmitter (setting the TXEN to zero) will not become effective

until ongoing and pending transmissions are completed, i.e., when the Transmit Shift

abled, the Transmitter will no longer override the TxDn pin.

ATMEGA640 Datasheet(PDF) 218 Page - ATMEL Corporation