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P90CE201 Datasheet(PDF) 6 Page - NXP Semiconductors

Part # P90CE201
Description  16-bit microcontroller
PDF  77 Pages
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Manufacturer  PHILIPS [NXP Semiconductors]
Direct Link  http://www.nxp.com
Logo PHILIPS - NXP Semiconductors

P90CE201 Datasheet(HTML) 6 Page - NXP Semiconductors

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August 1993
6
Philips Semiconductors
Product specification
16-bit microcontroller
P90CE201
4.2
Pin description
Table 1
QFP64 package.
MNEMONIC
TYPE
PIN NO.
FUNCTION
RXD
I/O
1
Receive Data. RXD is the data input for the UART interface.
SDA2
I/O
2
Serial Data 2 (open drain). SDA2 is the data signal for the second
I2C-bus serial interface.
SCL2
I/O
3
Serial Clock 2 (open drain). SCL2 is the clock signal for the second
I2C-bus serial interface.
GP7/SDA1
GP6/SCL1
GP0
GP1
GP2
GP3
GP4
GP5/T1
I/O
4
5
6
7
8
9
10
11
General Purpose Port (active HIGH, 3-state). The alternative functions
are as follows. SCL1 is the clock signal for the first I2C-bus serial
interface. SDA1 is the data signal for the first I2C-bus serial interface.
T1 is the input pin for Timer 1.
A23/AP7
to
A16/AP0
I/O
12 to 15, 21,
22, 24, 23
Address Bus. Upper 8-bits of the address bus (A23 to A16). The unused
address bits can be selected as a quasi-bidirectional port (AP).
A15 to A0
O
25, 26, 28, 27,
34, 38, 32, 30,
29, 31, 33, 35,
37, 39, 40, 42
Address Bus. Lower 16-bits of the address bus.
XTAL2
O
16
Oscillator output. Not connected if an external clock generator is used.
XTAL1
I
17
Oscillator input. XTAL1 can also be used as an external clock input if
an external clock generator is used.
VDD1
−
18
Supply voltage. For internal logic, address bus, data bus, RWN,
CSRAMN, CSROMN, XTAL1 and XTAL2.
VSS1
−
19
Ground. For internal logic, address bus, data bus, RWN, CSRAMN,
CSROMN, XTAL1 and XTAL2.
R/WN
O
20
Read (active HIGH)/Write (active LOW). This controls the direction of
data flow.
CSROMN
O
36
Chip Select ROM (active LOW). This signal selects external ROM.
D0 to D7
O
44, 46, 48, 49,
47, 45, 43, 41
Data Bus. 8-bit data bus.
CSRAMN
O
50
Chip Select RAM (active LOW). This signal enables external RAM.
VSS2
−
51
Ground. For all other periphery pins (quiet port).
VDD2
−
52
Supply voltage. For all other periphery pins (quiet port).
RESET
I
53
Reset (active HIGH). Input pin for an external reset.
T0
I
54
Timer 0. Input pin for cycle and event counting using Timer 0.
T2
I
55
Timer 2. Input pin for cycle and event counting using Timer 2.



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