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P90CE201 Datasheet(PDF) 32 Page - NXP Semiconductors |
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P90CE201 Datasheet(HTML) 32 Page - NXP Semiconductors |
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32 / 77 page ![]() August 1993 32 Philips Semiconductors Product specification 16-bit microcontroller P90CE201 7.2 Instruction timing This data assumes that both memory read and write cycle times are four internal clock periods (no additional wait states). Additional wait states for memory accesses have to be added to the total instruction time. Accesses to registers listed in the Register Map are only three clock periods, therefore one clock period can be subtracted for each access to such a register. However, access to the UART registers takes up to ten clock periods due to synchronization. Consequently, ten clock periods have to be added for UART register accesses. Table 17 Effective address calculation times. Note 1. The number of bus read and write cycles are shown in parentheses as (R/W). Table 18 MOVE Byte and Move Word instruction clock periods. SOURCE ADDRESSING MODE BYTE, WORD LONG Rn Data Address Register Direct 0 (0/0) 0 (0/0) (An) Address Register Indirect 4 (1/0) 8 (2/0) (An) + Address Register Indirect postincrement 4 (1/0) 8 (2/0) −(An) Address Register Indirect predecrement 7 (1/0) 11 (2/0) d(An) Address Register Indirect Displacement 11 (2/0) 15 (3/0) d(An, Xi) Address Register Indirect with Index 14 (2/0) 18 (3/0) xxx.S Absolute Short 8 (2/0) 12 (3/0) xxx.L Absolute Long 12 (3/0) 16 (4/0) d(PC) Program Counter with Displacement 11 (2/0) 15 (3/0) d(PC, Xi) Program Counter with Index 14 (2/0) 18 (3/0) #xxx Immediate 4 (1/0) 8 (2/0) SOURCE Rn (An) (An) +−(An) d(An) d(An,Xi) xxx.S xxx.L Rn 7 (1/0) 11 (1/1) 11 (1/1) 14 (1/1) 18 (1/1) 21 (1/1) 15 (1/1) 19 (1/1) (An) 11 (2/0) 15 (2/1) 15 (2/1) 18 (2/1) 22 (2/1) 25 (2/1) 19 (2/1) 23 (2/1) (An) + 11 (2/0) 15 (2/1) 15 (2/1) 18 (2/1) 22 (2/1) 25 (2/1) 19 (2/1) 23 (2/1) −(An) 14 (2/0) 18 (2/1) 18 (2/1) 22 (2/1) 25 (2/1) 28 (2/1) 22 (2/1) 26 (2/1) d(An) 18 (3/0) 22 (3/1) 22 (3/1) 25 (3/1) 29 (3/1) 32 (3/1) 26 (3/1) 30 (3/1) d(An,Xi) 21 (3/0) 25 (3/1) 25 (3/1) 28 (3/1) 32 (3/1) 35 (3/1) 29 (3/1) 33 (3/1) xxx.S 15 (3/0) 19 (3/1) 19 (3/1) 22 (3/1) 26 (3/1) 29 (3/1) 23 (3/1) 27 (3/1) xxx.L 19 (4/0) 23 (4/1) 23 (4/1) 26 (4/1) 30 (4/1) 33 (4/1) 27 (4/1) 31 (4/1) d(PC) 18 (3/0) 22 (3/1) 22 (3/1) 25 (3/1) 29 (3/1) 32 (3/1) 26 (3/1) 30 (3/1) d(PC,Xi) 21 (3/0) 25 (3/1) 25 (3/1) 28 (3/1) 32 (3/1) 35 (3/1) 29 (3/1) 33 (3/1) #xxx 11 (2/0) 15 (2/1) 15 (2/1) 18 (2/1) 22 (2/1) 25 (2/1) 19 (2/1) 23 (2/1) |
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