P90CE201 datasheet(13/77 Pages) PHILIPS

13 / 77 page

August 1993

Philips Semiconductors

Product speciﬁcation

16-bit microcontroller

P90CE201

5.4.2

MULTIPLE EXCEPTIONS

As two or more exceptions can occur simultaneously,

exceptions are grouped in order of priority; as is shown in

Table 3.

5.4.3

INSTRUCTION TRAPS

Traps are exceptions caused by instructions arising either

from CPU recognition of abnormal conditions during

instruction execution or from instructions whose normal

behaviour is to cause traps.

Some instructions are used specifically to generate traps.

The TRAP instruction always forces an exception, and is

useful for implementing system calls for user programs.

The TRAPV and CHK instructions force an exception if the

user program detects a run-time error, possibly an

arithmetic overflow or a subscript out of bounds. The

signed divide (DIVS) and unsigned divide (DIVU)

instructions will force an exception if a divide-by-zero

operation is attempted.

5.4.4

ILLEGAL AND UNIMPLEMENTED INSTRUCTIONS

Illegal instruction is the term used to refer to any word that

is not the first word of a legal instruction. During instruction

execution, if such an instruction is fetched, an illegal

instruction exception occurs. Words with bits 15 to 12

equal to 1010 or 1111 are defined as unimplemented

instructions and separate exception vectors are allocated

to these patterns for efficient emulation. This facility allows

the operating system to detect program errors, or to

emulate unimplemented instructions in software.

5.4.5

PRIVILEGE VIOLATIONS

To provide system security, various instructions are

privileged and any attempt to execute one of the privileged

and any attempt to execute one of the privileged

instructions while the CPU is in the user state causes an

exception. The privileged instructions are:

• STOP

• RESET

• RTE

• MOVE TO SR

• AND (word) immediate to SR

• EOR (word) immediate to SR

• OR (word) immediate to SR

• MOVE USP.

5.4.6

TRACING

The CPU includes a facility to trace instructions one by one

to assist in program development. In the trace state, after

each instruction is executed, an exception is forced so that

a debugging program can monitor execution of the

program under test.

The trace facility uses the T-bit in the supervisor part of the

Status Register. If the T-bit is cleared, tracing is disabled

and instructions execute normally. If the T-bit is set at the

beginning of the execution of an instruction, a trace

exception will be generated after that instruction is

executed. If the instruction is not executed, either because

of an interrupt, or because the instruction is illegal or

privileged, the trace exception does not occur. Also, the

trace exception does not occur if the instruction is aborted

by a reset, bus error, or address error exception. If the

instruction is executed and an interrupt is pending, the

trace exception is processed before the interrupt. If the

execution of an instruction forces an exception, the forced

exception is processed before the trace exception.

As an extreme illustration of the above rules, consider the

arrival of an interrupt during the execution of a TRAP

instruction while tracing is enabled. First the trap exception

is processed, then the trace exception, and finally the

interrupt is processed. Instruction execution resumes in

the interrupt handling routine.

Table 3

Exception grouping and priority.

GROUP

EXCEPTION

PROCESSING

RESET, ADDRESS ERROR

BUS ERROR

Exception processing begins at the next machine cycle.

TRACE, INTERRUPT,

ILLEGAL, PRIVILEGE

Exception processing begins before the next instruction.

TRAP, TRAPV, CHK, ZERO,

DIVIDE, FORMAT ERROR

Exception processing is started through normal instruction

execution.

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