PCF8820 datasheet(7/60 Pages) PHILIPS

7 / 60 page

2000 Dec 07

Philips Semiconductors

Product speciﬁcation

× 101 Grey-scale/ECB colour dot matrix

LCD driver

PCF8820

6.2.12

SLAVE ADDRESS INPUTS

These inputs (SA0 and SA1) allow up to four PCF8820

drivers to be controlled on the same I2C-bus. Inputs SA0

and SA1 represent respectively bit 0 and bit 1 of the slave

address.

6.2.13

OSCILLATOR SIGNAL INPUT

Pad OSC must be connected directly to VDD1 when the

on-chip oscillator is used. No external components are

required. It should be noted that any voltage drop of VDD1

may affect the performance of the on-chip oscillator.

An external clock must be connected to input OSC.

6.2.14

EXTERNAL RESET INPUT

A LOW-level on input RES initializes the chip.

6.2.15

TEST PADS

The test pads (T1, T2, T3, T4, T5 and T6) must not be

accessible to the user.

Pads T1, T3 and T4 must be connected to VSS1, pad T5

must be connected to VDD1, and pads T2 and T6 must be

left open-circuit.

FUNCTIONAL DESCRIPTION

7.1

Oscillator

The on-chip oscillator provides the clock signal for the LCD

system. The clock mode is controlled via the I2C-bus

interface. A clock signal must always be present, except in

the Power-down mode, to prevent the LCD entering a

DC state.

7.2

I2C-bus interface controller

The I2C-bus interface controller receives and executes the

commands sent via the I2C-bus. The PCF8820 acts as an

I2C-bus slave receiver/transmitter and therefore it cannot

control the bus communication.

7.3

Input ﬁlters

RC low-pass filters are provided on inputs SDA_IN, SCL

and RES to enhance noise immunity in electrically

adverse environments.

7.4

Display Data RAM (DDRAM)

The PCF8820 contains a 67

× 101 × 2-bit static RAM,

which stores the display data. The RAM comprises

17 banks of 101 bytes (17

× 101 × 8 bits). Not all of the

last bank is implemented. During RAM access, data is

transferred to the RAM via the I2C-bus interface controller.

7.5

Timing generator

The timing generator produces the various signals

required to drive the internal circuitry. Internal chip

operation is not affected by operations on the I2C-bus.

7.6

Address counter

The address counter generates write addresses to the

DDRAM. During a write operation, display data is stored at

the addressed locations.

7.7

Display address counter

The display address counter generates read addresses to

the DDRAM. During a read operation, display data is read

out to the LCD.

7.8

Command decoder

The command decoder receives command words which

are followed by data byte(s) from the I2C-bus. The

command decoder identifies the command words and

determines the destination for the data byte(s).

7.9

Column driver outputs

The LCD driver section has 101 outputs (C0 to C100)

which should be connected directly to the column drive

inputs of the LCD. The column driver signals are

generated in accordance with the multiplexed row signals

and with the data in the display data latch.

The programmed grey-scale levels are built-up in the LCD

over four frames (N11,N12,N13 and N14) as shown in

Figs 3, 4 and 5.

7.10

Row driver outputs

The LCD driver section has 67 outputs (R0 to R66) which

should be connected directly to the row drive inputs of the

LCD. The row driver signals are generated in accordance

with the selected LCD drive mode.

PCF8820 Datasheet(PDF) 7 Page - NXP Semiconductors

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