PCF8820 datasheet(24/60 Pages) PHILIPS

24 / 60 page

2000 Dec 07

Philips Semiconductors

Product speciﬁcation

× 101 Grey-scale/ECB colour dot matrix

LCD driver

PCF8820

8.1.1

POWER-DOWN MODE

During power-down (bit PD = 1) all static currents are

switched off (no internal oscillator, no timing, no LCD

segment drive system) and all LCD outputs are internally

connected to VSS.

To decrease the voltage at VLCDOUT very fast the following

features can be used:

• Select the direct drive mode by setting bit DM = 1

resulting in VLCDOUT =VDD2

• Select the non direct drive mode by setting bit DM = 0,

resulting in VLCDOUT = 0 V (output high-impedance).

During power-down:

• All LCD outputs at VSS (display off)

• Oscillator is off

• Intermediate bias voltage generator is off

• High voltage generator is disabled; however, the status

of bit HVE is unchanged (see Table 8)

• An external VLCD can be disconnected from VLCDIN

• The I2C-bus is operational; commands can be executed

• DDRAM contents is not cleared; DDRAM data can be

written

• Register settings remain unchanged

• Temperature measurement is not possible.

8.1.2

PARTIAL SCREEN MODE

Partial screen mode allows data to be displayed of

DDRAM bank 0 to 1 on the first 8 rows or bank 14 to 15 on

the last 8 rows, depending on the status of

bits DP2 to DP0.

If bit MY = 0, data is displayed either on rows 0 to 7 (first

8 rows) or on rows 56 to 63 (last 8 rows).

If bit MY = 1, data is displayed either on rows 66 to 59 (first

8 rows) or on rows 10 to 3 (last 8 rows).

The partial screen mode also allows VLCDIN to be reduced

to save power.

Frame frequency calibration is not allowed in the partial

screen mode.

8.1.3

Y-ADDRESS OF DDRAM

Bits Y4 to Y0 define the Y-address of the DDRAM.

Table 4

Y-address

8.1.4

BIAS SYSTEM

Different LCD bias voltage settings are required at

different multiplex rates. The status of bits BS2 to BS0 and

bit BS1/2 select different ‘bias systems’ which determine

the intermediate bias voltage levels between

VLCDIN and VSS1. It should be noted that the bias system

selected by bit BS1/2 is independent of the bias systems

selected by bits BS2 to BS0.

A value ‘n’ attributed to each bias system is used to

calculate these levels (see Table 5).

The optimum value for ‘n’ is given by:

where

M is the multiplex rate.

Table 6 shows how bias voltage levels are calculated for

three of the available bias systems using supported ‘n’

values.

RAM BANK

00000

bank 0

00001

bank 1

00010

bank 2

00011

bank 3

00100

bank 4

00101

bank 5

00110

bank 6

00111

bank 7

01000

bank 8

01001

bank 9

01010

bank 10

01011

bank 11

01100

bank 12

01101

bank 13

01110

bank 14

01111

bank 15

10000

bank 16

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