PCF8820 datasheet(16/60 Pages) PHILIPS

16 / 60 page

2000 Dec 07

Philips Semiconductors

Product speciﬁcation

× 101 Grey-scale/ECB colour dot matrix

LCD driver

PCF8820

7.18.3

SYSTEM CONFIGURATION

Thd system components are defined below (see Fig.13):

• Transmitter: the device which sends data to the bus

• Receiver: the device which receives data from the bus

• Master: the device which initiates a transfer, generates

clock signals and terminates a transfer

• Slave: the device addressed by a master

• Multi-master: more than one master can attempt to

control the bus at the same time without corrupting the

message

• Arbitration: procedure to ensure that, if more than one

master simultaneously tries to control the bus, only one

is allowed to do so and the message is not corrupted

• Synchronization: procedure to synchronize the clock

signals of two or more devices.

7.18.4

ACKNOWLEDGE

Each 8-bit data byte transferred over the bus must be

followed by an acknowledge bit (see Fig.14).

During the acknowledge clock pulse a HIGH-level signal is

put on the bus by the transmitter.

A slave receiver which is addressed must generate an

acknowledge bit after the reception of each data byte.

A master receiver must generate an acknowledge bit after

receiving a data byte that has been clocked out of the

slave transmitter. The device that acknowledges must

pull-down the SDA line to a LOW-level during the

acknowledge clock pulse. Set-up and hold times must be

taken into consideration to ensure that the SDA line is

stable during the HIGH period of the acknowledge related

clock pulse.

A master receiver must signal an end-of-data to the slave

transmitter by not generating an acknowledge bit on the

last byte that has been clocked out of the slave transmitter.

In this event the slave transmitter must leave the data line

HIGH to allow the master to generate a STOP condition.

For the PCF8820 the acknowledge bit is output at

pad SDA_OUT.

MGA807

SDA

SCL

MASTER

TRANSMITTER/

RECEIVER

MASTER

TRANSMITTER

SLAVE

TRANSMITTER/

RECEIVER

SLAVE

RECEIVER

MASTER

TRANSMITTER/

RECEIVER

Fig.13 System configuration.

handbook, full pagewidth

MBC602

START

condition

clock pulse for

acknowledgement

not acknowledge

acknowledge

DATA OUTPUT

BY TRANSMITTER

DATA OUTPUT

BY RECEIVER

SCL FROM

MASTER

Fig.14 Acknowledgement on the I2C-bus.

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