PCF8820 datasheet(28/60 Pages) PHILIPS

28 / 60 page

2000 Dec 07

Philips Semiconductors

Product speciﬁcation

× 101 Grey-scale/ECB colour dot matrix

LCD driver

PCF8820

8.1.9

DIRECT DRIVE MODE

The voltage multiplier is in the direct drive mode

(VLCDOUT =VDD2) in the following settings (see Table 8):

• If bit DM = 1 and Power-down mode (bit PD = 1)

• If bit DM = 1 and display off mode (bit DOF = 1)

• If bit DM = 1 and high voltage generator is disabled

(bit HVE = 0).

It is recommended to always select the direct drive mode

before switching on the voltage multiplier. This is a feature

which can be used to reduce VLCDOUT very quickly, or to

avoid high current when the voltage multiplier starts up.

Output VLCDOUT is high-impedance when bit DM = 0 and

bit PD = 1, bit DM = 0 and bit DOF = 0 or when bit DM = 0,

bit PD = 0 and bit HVE = 0.

Table 8

Output VLCDOUT as a function of bits DM, HVE,

PD and DOF; note 1

Note

1. X = don’t care.

8.1.10

FRAME FREQUENCY CALIBRATION

The PCF8820 uses on-chip software to calibrate the frame

frequency. After reset, the frame frequency calibration is

disabled (bit OC = 0). Frame frequency calibration can

only be performed if the PCF8820 is not in Power-down

mode or in the partial screen mode.

The calibration is initiated by setting bit OC = 1 and is

stopped by setting bit OC = 0. The time between

calibration start and stop must be 190

µs to give a frame

frequency of 77 Hz (typical value).

All other commands are allowed during a calibration.

The frame frequency calibration uses a pre-divider which

has a range from 1 : 1 to 1 : 15. The default ratio after reset

is 1 : 4. The calibration period determines the pre-divider

ratio for the oscillator frequency or external clock signal.

The resulting frame frequency is calculated by the

equation:

where fclk can be either the internal oscillator clock signal

or an external clock signal source.

Figure 21 shows the resulting frame frequency at different

clock frequencies and at different pre-divider ratios, for a

calibration period of 190

µs.

The frame frequency calibration can also be used to set

the frame frequency to a lower than typical value with a

corresponding reduction in current consumption. The

necessary calibration period (time between calibration

start and stop) can be estimated by the equation:

where tcal is the calibration time in µs and fframe is the

desired frame frequency in Hz.

Figure 22 shows the resulting frame frequency as a

function of the calibration period at different pre-divider

ratios at a clock frequency of 336 kHz.

8.2

Reset and initialization

After power-on the content of all internal registers

including the DDRAM are in an undefined state. A reset

pulse must be applied within a specified time to reset all

internal registers. A reset can be achieved by applying an

external reset pulse (active LOW) to pad RES. When reset

occurs within the specified time all internal registers are

reset, however the DDRAM is still undefined.

After VDD1 has reached its minimum value, the RES input

level must be

≤0.3VDD1 after a maximum time tsu

(see Fig.24).

After reset the state of the PCF8820 is as follows:

• Default values of bits and registers as seen in Table 3

• All row and column outputs are at VSS (display off)

• VLCDOUT is high-impedance

• RAM data is undefined.

HVE

DOF

VLCDOUT

high Z

1000

VDD2

1X1X

VDD2

internally generated VLCD

frame

clk

1088

-------------

pre-divider ratio

[]

cal

77 (Hz)

190

µs

()

frame

-------------------------------------------------

PCF8820 Datasheet(PDF) 28 Page - NXP Semiconductors

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