DSP56857E datasheet(22/53 Pages) FREESCALE

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56857 Technical Data, Rev. 6

Freescale Semiconductor

Table 4-1 Absolute Maximum Ratings

Characteristic

Symbol

Min

Max

Unit

Supply voltage, core

VDD1

1. VDD must not exceed VDDIO

VSS – 0.3

VSS + 2.0

Supply voltage, IO

Supply voltage, analog

VDDIO2

2. VDDIO and VDDA must not differ by more that 0.5V

VSSIO – 0.3

VSSA – 0.3

VSSIO + 4.0

VDDA + 4.0

Digital input voltages

Analog input voltages (XTAL, EXTAL)

VIN

VINA

VSSIO – 0.3

VSSA – 0.3

VSSIO + 5.5

VDDA + 0.3

Current drain per pin excluding VDD, GND

—

Junction temperature

-40

120

°C

Storage temperature range

TSTG

-55

150

°C

Table 4-2 Recommended Operating Conditions

Characteristic

Symbol

Min

Max

Unit

Supply voltage for Logic Power

VDD

1.62

1.98

Supply voltage for I/O Power

VDDIO

3.0

3.6

Supply voltage for Analog Power

VDDA

3.0

3.6

Ambient operating temperature

-40

°C

PLL clock frequency1

1. Assumes clock source is direct clock to EXTAL or crystal oscillator running 2-4MHz. PLL must be enabled, locked, and

selected. The actual frequency depends on the source clock frequency and programming of the CGM module.

fpll

—240

MHz

Operating Frequency2

2. Master clock is derived from on of the following four sources:

fclk = fxtal when the source clock is the direct clock to EXTAL

fclk = fpll when PLL is selected

fclk = fosc when the source clock is the crystal oscillator and PLL is not selected

fclk = fextal when the source clock is the direct clock to EXTAL and PLL is not selected

fop

—120

MHz

Frequency of peripheral bus

fipb

—60

MHz

Frequency of external clock

fclk

—240

MHz

Frequency of oscillator

fosc

MHz

Frequency of clock via XTAL

fxtal

—240

MHz

Frequency of clock via EXTAL

fextal

MHz

DSP56857E Datasheet(PDF) 22 Page - Freescale Semiconductor, Inc

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