DSP56857E datasheet(15/53 Pages) FREESCALE

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Introduction

56857 Technical Data, Rev. 6

Freescale Semiconductor

TIO3

GPIOG3

Input/Output

Timer Input/Output (TIO3)—This pin can be independently configured to

be either a timer input source or an output flag.

Port G GPIO (3)—This pin is a General Purpose I/O (GPIO) pin that can

individually be programmed as an input or output pin.

IRQA

Input

External Interrupt Request A and B—The IRQA and IRQB inputs are

asynchronous external interrupt requests that indicate that an external

device is requesting service. A Schmitt trigger input is used for noise

immunity. They can be programmed to be level-sensitive or

negative-edge- triggered. If level-sensitive triggering is selected, an

external pull-up resistor is required for Wired-OR operation.

IRQB

MODE A

GPIOH0

Input

Input/Output

Mode Select (MODE A)—During the bootstrap process MODE A selects

one of the eight bootstrap modes.

Port H GPIO (0)—This pin is a General Purpose I/O (GPIO) pin after the

bootstrap process has completed.

MODE B

GPIOH1

Input

Input/Output

Mode Select (MODE B)—During the bootstrap process MODE B selects

one of the eight bootstrap modes.

Port H GPIOH1—This pin is a General Purpose I/O (GPIO) pin after the

bootstrap process has completed.

MODE C

GPIOH2

Input

Input/Output

Mode Select (MODE C)—During the bootstrap process MODE C selects

one of the eight bootstrap modes.

Port H GPIO (2)—This pin is a General Purpose I/O (GPIO) pin after the

bootstrap process has completed.

RESET

Input

Reset (RESET)—This input is a direct hardware reset on the processor.

When RESET is asserted low, the controller is initialized and placed in

the Reset state. A Schmitt trigger input is used for noise immunity. When

the RESET pin is deasserted, the initial chip operating mode is latched

from the MODE A, MODE B, and MODE C pins.

To ensure complete hardware reset, RESET and TRST should be

asserted together. The only exception occurs in a debugging

environment when a hardware reset is required and it is necessary not to

reset the JTAG/Enhanced OnCE module. In this case, assert RESET, but

do not assert TRST.

RSTO

Output

Reset Output (RSTO)—This output is asserted on any reset condition

(external reset, low voltage, software or COP).

RXD0

GPIOE0

Input

Input/Output

Serial Receive Data 0 (RXD0)—This input receives byte-oriented serial

data and transfers it to the SCI 0 receive shift register.

Port E GPIO (0)—This pin is a General Purpose I/O (GPIO) pin that can

individually be programmed as input or output pin.

Table 3-1 56857 Signal and Package Information for the 100-pin LQFP (Continued)

Pin No.

Signal Name

Type

Description

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