DSP56857E datasheet(29/53 Pages) FREESCALE

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Reset, Stop, Wait, Mode Select, and Interrupt Timing

56857 Technical Data, Rev. 6

Freescale Semiconductor

4.6 Reset, Stop, Wait, Mode Select, and Interrupt Timing

Table 4-6 PLL Timing

Operating Conditions: VSS = VSSIO = VSSA = 0 V, VDD = 1.62-1.98V, VDDIO = VDDA = 3.0–3.6V, TA = –40° to +120°C, CL ≤ 50pF, fop = 120MHz

Characteristic

Symbol

Min

Typ

Max

Unit

External reference crystal frequency for the PLL1

1. An externally supplied reference clock should be as free as possible from any phase jitter for the PLL to work correctly.

The PLL is optimized for 4MHz input crystal.

fosc

MHz

PLL output frequency

fclk

—

240

MHz

PLL stabilization time 2

2. This is the minimum time required after the PLL setup is changed to ensure reliable operation.

tplls

—1

Table 4-7 Reset, Stop, Wait, Mode Select, and Interrupt Timing1, 2

Operating Conditions: VSS = VSSIO = VSSA = 0 V, VDD = 1.62-1.98V, VDDIO = VDDA = 3.0–3.6V, TA = –40° to +120°C, CL ≤ 50pF, fop = 120MHz

1. In the formulas, T = clock cycle. For fop = 120MHz operation and fipb = 60MHz, T = 8.33ns.

2. Parameters listed are guaranteed by design.

Characteristic

Symbol

Typ Min

Typ

Max

Unit

See Figure

Minimum RESET Assertion Duration3

3. At reset, the PLL is disabled and bypassed. The part is then put into Run mode and tclk assumes the period of the source clock,

txtal, textal or tosc.

tRA

—

4-10

Edge-sensitive Interrupt Request Width

tIRW

1T + 3

—

4-11

IRQA, IRQB Assertion to General Purpose Output Valid,

caused by first instruction execution in the interrupt

service routine

tIG

18T

—

4-12

IRQA Width Assertion to Recover from Stop State

tIW

—

4-13

Delay from IRQA Assertion to Fetch of first instruction

(exiting Stop)4

Fast5

Normal6, 7

4. This interrupt instruction fetch is visible on the pins only in Mode 3.

5. Fast stop mode:

Fast stop recovery applies when external clocking is in use (direct clocking to XTAL) or when fast stop mode recovery is request-

ed (OMR bit 6 is set to 1). In both cases the PLL and the master clock are unaffected by stop mode entry. Recovery takes one less

cycle and tclk will continue with the same value it had before stop mode was entered.

6. Normal stop mode:

As a power saving feature, normal stop mode disables and bypasses the PLL. Stop mode will then shut down the master clock,

recovery will take an extra cycle (to restart the clock), and tclk will resume at the input clock source rate.

tIF

—

13T

25ET

4-13

RSTO pulse width7

normal operation

internal reset mode

7. ET = External Clock period; for an external crystal frequency of 4MHz, ET=250ns.

tRSTO

128ET

8ET

—

4-14

DSP56857E Datasheet(PDF) 29 Page - Freescale Semiconductor, Inc

DSP56857E Datasheet(HTML) 29 Page - Freescale Semiconductor, Inc

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