DSP56857E datasheet(24/53 Pages) FREESCALE

24 / 53 page

56857 Technical Data, Rev. 6

Freescale Semiconductor

Figure 4-1 Maximum Run IDDTOTAL vs. Frequency (see Notes 1. and 5. in Table 4-4)

VDDIO supply current (I/O circuity)

Run5

Deep Stop2

IDDIO

—40

1.5

VDDA supply current (analog circuity)

Deep Stop2

IDDA

—60

120

μA

Low Voltage Interrupt6

VEI

—

2.5

2.85

Low Voltage Interrupt Recovery Hysteresis

VEIH

—50

—

Power on Reset7

POR

—

1.5

2.0

Note:

Run (operating) IDD measured using external square wave clock source (fosc = 4MHz) into XTAL. All inputs 0.2V from rail;

no DC loads; outputs unloaded. All ports configured as inputs; measured with all modules enabled. PLL set to 240MHz out.

Running Core, performing 50% NOP and 50% FIR. Clock at 120 MHz.

Deep Stop Mode - Operation frequency = 4 MHz, PLL set to 4 MHz, crystal oscillator and time of day module operating.

Light Stop Mode - Operation frequency = 120 MHz, PLL set to 240 MHz, crystal oscillator and time of day module operating.

IDD includes current for core logic, internal memories, and all internal peripheral logic circuitry.

Running core and performing external memory access. Clock at 120 MHz.

When VDD drops below VEI max value, an interrupt is generated.

Power-on reset occurs whenever the digital supply drops below 1.8V. While power is ramping up, this signal remains active

for as long as the internal 2.5V is below 1.8V no matter how long the ramp up rate is. The internally regulated voltage is typically

100 mV less than VDD during ramp up until 2.5V is reached, at which time it self-regulates.

Table 4-4 DC Electrical Characteristics (Continued)

Operating Conditions: VSS = VSSIO = VSSA = 0 V, VDD = 1.62-1.98V, VDDIO = VDDA = 3.0–3.6V, TA = –40° to +120°C, CL ≤ 50pF, fop = 120MHz

Characteristic

Symbol

Min

Typ

Max

Unit

120

150

100

120

EMI Mode5

MAC Mode1

DSP56857E Datasheet(PDF) 24 Page - Freescale Semiconductor, Inc

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