DSP56857E datasheet(20/53 Pages) FREESCALE

20 / 53 page

56857 Technical Data, Rev. 6

Freescale Semiconductor

TRST

Input

Test Reset (TRST)—As an input, a low signal on this pin provides a reset

signal to the JTAG TAP controller. To ensure complete hardware reset,

TRST should be asserted whenever RESET is asserted. The only

exception occurs in a debugging environment, since the Enhanced

OnCE/JTAG module is under the control of the debugger. In this case it is

not necessary to assert TRST when asserting RESET. Outside of a

debugging environment RESET should be permanently asserted by

grounding the signal, thus disabling the Enhanced OnCE/JTAG module

on the device.

Note:

For normal operation, connect TRST directly to VSS. If the design is to

be used in a debugging environment, TRST may be tied to VSS through a 1K

resistor.

Input/Output

Debug Event (DE)—This is an open-drain, bidirectional, active low

signal. As an input, it is a means of entering debug mode of operation

from an external command controller. As an output, it is a means of

acknowledging that the chip has entered debug mode.

This pin is connected internally to a weak pull-up resistor.

Table 3-1 56857 Signal and Package Information for the 100-pin LQFP (Continued)

Pin No.

Signal Name

Type

Description

DSP56857E Datasheet(PDF) 20 Page - Freescale Semiconductor, Inc