33389 datasheet(30/49 Pages) FREESCALE

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Analog Integrated Circuit Device Data

Freescale Semiconductor

33389

FUNCTIONAL DEVICE OPERATION

LOGIC COMMANDS AND REGISTERS

Figure 15. Current vs Temp and Batt Voltage

LOGIC COMMANDS AND REGISTERS

SPI Introduction

This SPI system is flexible enough to communicate directly

with numerous standard peripherals and MCUs available

from Motorola and other semiconductor manufacturers. SPI

reduces the number of pins necessary for input/output on the

33389. The SPI system of communication consists of the

MCU transmitting, and in return, receiving one data bit of

information per clock cycle. Data bits of information are

simultaneously transmitted by one pin, Microcontroller Out

Serial In (MOSI), and received by another pin, Microcontroller

In Serial Out (MISO), of the MCU. Figure 16 illustrates the

basic SPI configuration between an MCU and one 33389.

The SPI serial operation is guaranteed to 2.0 MHz.

Figure 16. SPI Interface with Microcontroller

CS PIN

The system MCU selects the MC33389 to be

communicated with, through the use of the CS pin. Whenever

the pin is in logic low state, data can be transferred from the

MCU to the MC33389 and vice versa. Clocked-in data from

the MCU is transferred from the MC33389 shift register and

latched into the addressed registers on the rising edge of the

CS signal if the read/write bit is set and the parity check was

successful.

The CS pin controls the output driver of the serial output

pin. Whenever the CS pin goes to a logic low state, the MISO

pin output driver is enabled allowing information to be

transferred from the MC33389 to the MCU. To avoid any

spurious data, it is essential that the high-to-low transition of

the CS signal occur only when SCLK is in a logic low state.

SCLK PIN

The system clock pin (SCLK) clocks the internal shift

registers of the MC33389. The serial input pin (MOSI)

accepts data into the input shift register on the falling edge of

the SCLK signal while the serial output pin (MISO) shifts data

information out of the shift register on the rising edge of the

SCLK signal. False clocking of the shift register must be

avoided to guarantee validity of data. It is essential that the

SCLK pin be in a logic low state whenever chip select bar pin

(CS) makes any transition. For this reason, it is

recommended though not necessary, that the SCLK pin be

kept in a low logic state as long as the device is not accessed

(CS in logic high state). When CS is in a logic high state, any

signal at the SCLK and MOSI pin is ignored and MISO is

tristated (high impedance).

MOSI PIN

This pin is for the input of serial instruction data. MOSI

information is read in on the falling edge of SCLK. To

program the MC33389 by setting appropriate programming

registers, an sixteen bit serial stream of data is required to be

100

120

140

16 V

TEMPERATURE (°C)

-50

100

150

-25

125

160

180

12 V

6.0V

MOSI

SCLK

MISO

MOSI

MISO

MC68HCXX

33389

33389 Datasheet(PDF) 30 Page - Freescale Semiconductor, Inc

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