33389 datasheet(34/49 Pages) FREESCALE

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Analog Integrated Circuit Device Data

Freescale Semiconductor

33389

FUNCTIONAL DEVICE OPERATION

LOGIC COMMANDS AND REGISTERS

Figure 21. Microcontroller SPI Reading Data - Sequence C

Safety Concept

Because the SPI interface is an on-board interface without

any data fault detection capabilities, the SPI interface of the

33389 provides built-in fail save functions.

Address coding is based on increasing the Hamming

distance, parity check, and parity generation for data.

For the address and the read/write bits, only codes with a

Hamming distance < 2 will be used. So, any single bit failure

caused by disturbances will be recognized and handled.

When one bit toggles in the address field during the

transmission, no misbehavior occurs.

Additionally, validation registers are implemented to

confirm safety critical settings in the 33389, e.g. the Mode

Control Register MCR has its validation register, MCVR. To

change the appropriate settings, both registers must have the

same content to switch to another mode.

To increase data integrity, a parity check is used. A parity

module in the 33389 ascertains the parity of the data field and

compares the result with the received parity. When the parity

check is successfully passed, data will be written into the

addressed registers. The parity bits P3 to P0 results from the

logic following equations:

In case of error detection, the incoming data is not taken in

the SBC and an error flag is set in an SPI register.

SPI REGISTERS DESCRIPTIONS

Registers MCR and MCVR control the SBC mode. To

change the operating mode of the SBC, both registers must

have the same content. The order of writing the registers has

to be taken into account. To properly set the SBC mode,

MCR must be written first followed by the MCVR write. A write

operation sets the MCR and MCVR registers.

The Emergency mode is a regular mode.

A reset of both MCR and MCVR registers occurs when

RST = low and the SBC is set to Normal Request mode.

P1 P0 D3 D2 D1 D0

P3 P2

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

new parity + new data in

HC08/12 SPI read buffer

A5 A4 A3 A2 A1 A0

A3 A2 A1 A0

A5 A4

SBC SPI Data Register

Bit14 Bit13 Bit12 Bit11 Bit10 Bit9

Bit8

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

Bit15

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

HC08/12 SPI Data Register

old address + R/W

old data

old parity

P3 = D3

⊕ D0

(EX - OR)

P2 = D3

⊕ D2

P1 = D2

⊕ D1

P0 = D1

⊕ D0

Table 17. Mode Control Register (MCR)

Address

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

MCR

$000

MSR2

MSR1

MSR0

MCR2

MCR1

MCR0

RESET

—

33389 Datasheet(PDF) 34 Page - Freescale Semiconductor, Inc

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