33389 datasheet(32/49 Pages) FREESCALE

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Analog Integrated Circuit Device Data

Freescale Semiconductor

33389

FUNCTIONAL DEVICE OPERATION

LOGIC COMMANDS AND REGISTERS

Figure 17. SPI Communication Format

The SBC is accessible via the SPI interface in the Normal

Request mode, Normal mode, and Stand-by mode. In all

other modes (Sleep mode, Emergency mode), the voltage

supply for the microcontroller in permanently switched OFF

and the SBC input logic for MISO, MOSI, CS and SCLK isn’t

working (except SPI wake-up function in the Sleep mode).

Writing Data

To write data in a SPI register there are two, one-byte

transmissions to be performed. The first byte contains the

address of the register (MSB first) and the read/write bits

must be set to one. The second byte contains the new data

addressed by the previous byte (MSB first) and the parity

information. The calculation of the parity field P3-P0 has to

follow the equations:

Note: During the transmission of the two bytes the CS pin

remains 0. Please see Figure 18

Figure 18. Microcontroller SPI Writing Data

The SBC sends back the old address, R/W, parity, and

data information from a previous transmission. This data

contains no useful information (e.g. status). It shouldn’t be used.

In case of a wrong address field or parity mismatch, an

interrupt will be issued and the SBC retains the old state.

Reading Data

To read data from a dedicated register two, one-byte

transmissions have to be performed. The first byte contains

the address of the register (MSB first) and the read/write flags

setting to zero. The second byte needn’t contain valid data,

nevertheless, the parity calculation has to performed to avoid

an interrupt caused by a parity mismatch.

During a read operation the SBC sends back the old

address and R/W bits and the new data addressed by the first

transmitted byte starting with P3 after the last valid read/write

bit has been received.

Note: During the transmission of the two bytes the CS pin

remains zero.

A5 A4 A3 A2 A1 A0

D3 D2 D1 D0

P3 P2 P1 P0

Bit14 Bit13 Bit12 Bit11 Bit10 Bit9

Bit8

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

Bit15

address + R/W

data

parity

MOSI

MISO

P3 = D3

⊕ D0

(EX - OR)

P2 = D3

⊕ D2

P1 = D2

⊕ D1

P0 = D1

⊕ D0

A5 A4 A3 A2 A1 A0

D3 D2 D1 D0

P3 P2 P1 P0

A3 A2 A1 A0

A5 A4

SBC SPI Data Register

Bit14 Bit13 Bit12 Bit11 Bit10 Bit9

Bit8

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

Bit15

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

HC08/12 SPI Data Register

old address + R/W

old data

old parity

new address + R/W (1st byte)

new data + parity (2nd byte)

D3 D2 D1 D0

P3 P2 P1 P0

33389 Datasheet(PDF) 32 Page - Freescale Semiconductor, Inc

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