Analog Integrated Circuit Device Data

Freescale Semiconductor

37

33389

FUNCTIONAL DEVICE OPERATION

LOGIC COMMANDS AND REGISTERS

This register configures the wake-up level for the L0, L1, and L2 inputs. It reports the CAN wake-up and SPI (CS) wake-up

events during the Read operation.

This register reads back the wake input (L0, L1, L2) causing the SBC to wake-up.

Table 27. GSLR Bit Definition

GSLR1

GSLR0

Typical Ground Shift Level

0

0

0.7 V

0

1

-1.2 V

1

0

-1.7 V

1

1

-2.2 V

SHIFT

1 = Ground shift above the threshold selected by GSLR1 and GSLR2

0 = No ground shift

The SHIFT information is latched until a read operation of the GSLR register occurs. The GSLR register is set to 0 after power-ON

reset. A reset of GSLR1 and GSLR0 occurs when RST = Low.

TXDOM

0 = No failure on TX

1 = TX permanent dominant

Table 28. Wake-Up Input Control Register (WUICR)

Address

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

WUICR

$00C

R

SPIWU

BUSWU

WUCR1

WUICR0

W

RESET

—

—

—

—

0

0

0

0

Table 29. WUICR Bit Definition

WUICR1

WUICR0

Description

0

0

Wake-Up Inputs Disabled

0

1

Positive Edge Sensitive

1

0

Negative Edge Sensitive

1

1

Positive and Negative Sensitive

Table 30. WUICR Bit Definition

SPIWU

BUSWU

Description

0

0

No Wake-Up Events

0

1

Wake-Up Event on CAN Bus

1

0

Wake-Up Event on SPI Bus

The information is SPIWU and BUSWU is latched. Bits SPIWU and BUSWU will be reset by a read operation of the WUICR

register and are set to 0 after a power-ON reset. A reset of WUICR1 and WUICR0 occurs when RST = Low.

Table 31. Wake-Up Input Status Register (WUISR)

Address

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

WUISR

$00F

R

WUISR2

WUISR1

WUISR0

W

RESET

—

—

—

—

—

0

0

0