STPMIC25 datasheet(120/145 Pages) STMICROELECTRONICS

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6.8.16

NVM pull-down control shadow register 1 (NVM_PD_SHR1)

Table 96. NVM_PD_SHR1

BUCK4_PD[1:0]

BUCK3_PD[1:0]

BUCK2_PD[1:0]

BUCK1_PD[1:0]

R/W

•

Address: 0xA9

•

Default: Depends on the PMIC part number

•

Description: NVM pull-down control shadow register 1.

The content of this register is copied into BUCKS_PD_CR1 in the INIT&LOAD and the CHECK&LOAD states.

[7:6]

BUCK4_PD[1:0]: BUCK4 pull-down selection.

00: no pull-down

01: slow pull-down active when BUCK4 is disabled (EN = 0)

10: fast pull-down active when BUCK4 is disabled (EN = 0)

11: slow pull-down forced active

[5:4]

BUCK3_PD[1:0]: BUCK3 pull-down selection.

00: no pull-down

01: slow pull-down active when BUCK3 is disabled (EN = 0)

10: fast pull-down active when BUCK3 is disabled (EN = 0)

11: slow pull-down forced active

[3:2]

BUCK2_PD[1:0]: BUCK2 pull-down selection.

00: no pull-down

01: slow pull-down active when BUCK2 is disabled (EN = 0)

10: fast pull-down active when BUCK2 is disabled (EN = 0)

11: slow pull-down forced active

[1:0]

BUCK1_PD[1:0]: BUCK1 pull-down selection.

00: no pull-down

01: slow pull-down active when BUCK1 is disabled (EN = 0)

10: fast pull-down active when BUCK1 is disabled (EN = 0)

11: slow pull-down forced active

STPMIC25

DS14278 - Rev 3

page 120/145

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