STPMIC25 datasheet(130/145 Pages) STMICROELECTRONICS

130 / 145 page

6.8.26

NVM fail-safe shadow register 3 (NVM_FS_SHR3)

Table 106. NVM_FS_SHR3

reserved

FAIL_SAFE_LOCK_DIS

RST_FLT_CNT_TMR[1:0]

WDG_FLT_CNT_MAX[3:0]

R/W

•

Address: 0xB3

•

Default: Depends on the PMIC part number

•

Description: NVM fail-safe shadow register 3 (see Section 5.4.5).

[7]

reserved

[6]

FAIL_SAFE_LOCK_DIS: disable fail-safe lock state (pass through)

0: FAIL_SAFE_LOCK feature enabled (the PMIC stays in the FAIL_SAFE_LOCK state)

1: FAIL_SAFE_LOCK feature disabled (the PMIC passes through the FAIL_SAFE_LOCK state to go into the OFF state)

[5:4]

RST_FLT_CNT_TMR[1:0]: reset fault counter timer settings. When the timer elapses, it automatically clears all fault

counters (*_FLT_CNT)

00: disabled

01: 1 minute

10: 6 minutes

11: 60 minutes

[3:0]

WDG_FLT_CNT_MAX[3:0]: setting of the maximum number of occurrences triggered by a watchdog hard-fault source.

0000: 0 hard-faults allowed (the PMIC goes into the FAIL_SAFE_LOCK_STATE when the 1st hard-fault condition

occurs)

0001: 1 hard-fault allowed (PMIC goes into the FAIL_SAFE_LOCK_STATE when the 2nd hard-fault condition occurs)

…

1110: 14 hard-faults allowed (the PMIC goes into the FAIL_SAFE_LOCK_STATE when the 15th hard-fault condition

occurs)

1111: ∞ hard-faults allowed (fail-safe disabled: the PMIC always restarts when a hard-fault condition occurs)

STPMIC25

DS14278 - Rev 3

page 130/145

STPMIC25 Datasheet(PDF) 130 Page - STMicroelectronics