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STPMIC25 Datasheet(PDF) 131 Page - STMicroelectronics

Part # STPMIC25
Description  Highly integrated power management IC for microprocessor units
PDF  145 Pages
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Manufacturer  STMICROELECTRONICS [STMicroelectronics]
Direct Link  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

STPMIC25 Datasheet(HTML) 131 Page - STMicroelectronics

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6.8.27
NVM I²C device address shadow register (NVM_I2C_ADDR_SHR)
Table 107. NVM_I2C_ADD_SHR
7
6
5
4
3
2
1
0
LOCK_NVM
I²C_ADDR[6:0]
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
•
Address: 0xB5
•
Default: Depends on the PMIC part number
•
Description: NVM I²C device address shadow register.
The content of this register take effect after the NVM programming command, then the NVM reloads (INIT&LOAD
state or CHECK&LOAD state or NVM read command).
The LOCK_NVM bit takes effect on both shadow registers write and NVM programming command. A successful
program operation is enough to have the lock active (without any reload).
[7]
LOCK_NVM: NVM write access lock:
0: NVM write allowed
1: NVM write disabled
[6:0]
I²C_ADDR[6:0]: I²C device address.
6.8.28
NVM user free shadow register (NVM_USER_SHRx) (x = 1 to 2)
Table 108. NVM_USER_SHRx
7
6
5
4
3
2
1
0
NVM_USERx[7:0]
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
•
Address: 0xB6, 0xB7
•
Default: 0x00 (genuine PMIC) or user defined value
•
Description: User free shadow register 1 and 2.
Free usage scratch registers save end-product application data in the NVM.
It requires an NVM programing command to save content in the NVM.
[7:0]
NVM_USERx[7:0]: user defined value.
STPMIC25
Register descriptions
DS14278 - Rev 3
page 131/145



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