STPMIC25APQR datasheet(139/145 Pages) STMICROELECTRONICS

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6.5.14

LDO4 ALTERNATE mode control register (LDO4_ALT_CR) ...................... 102

6.5.15

REFDDR MAIN mode control register (REFDDR_MAIN_CR) ..................... 103

6.5.16

REFDDR ALTERNATE mode control register (REFDDR_ALT_CR) ................ 103

6.5.17

REFDDR PWRCTRL control register (REFDDR_PWRCTRL_CR) ................. 104

6.6

Interrupt registers ............................................................105

6.6.1

Interrupt management overview ........................................... 105

6.6.2

Interrupt pending register 1 (INT_PENDING_R1) .............................. 105

6.6.3

Interrupt pending register 2 (INT_PENDING_R2) .............................. 106

6.6.4

Interrupt pending register 3 (INT_PENDING_R3) .............................. 106

6.6.5

Interrupt pending register 4 (INT_PENDING_R4) .............................. 107

6.6.6

Interrupt clear registers (INT_CLEAR_Rx) (x = 1 to 4) .......................... 107

6.6.7

Interrupt mask registers (INT_MASK_Rx) (x = 1 to 4) ........................... 108

6.6.8

Interrupt source registers (INT_SRC_Rx) (x = 1 to 4) ........................... 108

6.6.9

Interrupt debug latch registers (INT_DBG_LATCH_Rx) (x = 1 to 4)................. 108

6.7

NVM registers ...............................................................109

6.7.1

NVM status register (NVM_SR) ........................................... 109

6.7.2

NVM control register (NVM_CR) ........................................... 110

6.8

NVM shadow registers ........................................................ 111

6.8.1

NVM main control shadow register 1 (NVM_MAIN_CTRL_SHR1) ................. 111

6.8.2

NVM main control shadow register 2 (NVM_MAIN_CTRL_SHR2) ................. 112

6.8.3

NVM rank shadow register 1 (NVM_RANK_SHR1)............................. 113

6.8.4

NVM rank shadow register 2 (NVM_RANK_SHR2)............................. 113

6.8.5

NVM rank shadow register 3 (NVM_RANK_SHR3)............................. 114

6.8.6

NVM rank shadow register 4 (NVM_RANK_SHR4)............................. 114

6.8.7

NVM rank shadow register 5 (NVM_RANK_SHR5)............................. 115

6.8.8

NVM rank shadow register 6 (NVM_RANK_SHR6)............................. 116

6.8.9

NVM rank shadow register 7 (NVM_RANK_SHR7)............................. 116

6.8.10

NVM rank shadow register 8 (NVM_RANK_SHR8)............................. 116

6.8.11

NVM BUCK mode shadow register 1 (NVM_BUCK_MODE_SHR1) ................ 117

6.8.12

NVM BUCK mode shadow register 2 (NVM_BUCK_MODE_SHR2) ................ 118

6.8.13

NVM BUCKx output voltage shadow register (NVM_BUCKx_VOUT_SHR) (x = 1 to 7) . 118

6.8.14

NVM LDOx shadow register (NVM_LDOx_SHR) (x = 2/5/6/7/8) ................... 119

6.8.15

NVM LDO3 control shadow register (NVM_LDO3_SHR) ........................ 119

6.8.16

NVM pull-down control shadow register 1 (NVM_PD_SHR1) ..................... 120

6.8.17

NVM pull-down control shadow register 2 (NVM_PD_SHR2) ..................... 121

6.8.18

NVM pull-down control shadow register 3 (NVM_PD_SHR3) ..................... 122

6.8.19

NVM BUCKs output current limitation shadow register 1 (NVM_BUCKS_IOUT_SHR1) . 123

6.8.20

NVM BUCKs output current limitation shadow register 2 (NVM_BUCKS_IOUT_SHR2) . 124

STPMIC25

Contents

DS14278 - Rev 3

page 139/145

STPMIC25APQR Datasheet(PDF) 139 Page - STMicroelectronics

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