PM3351-SW datasheet(42/268 Pages) PMC

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PM3351 ELAN 1X100

DATA SHEET

PMC-970113

ISSUE 3

SINGLE PORT FAST ETHERNET SWITCH

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE

memory data bus lines to specific values during reset, as described later; the resistor

values used are not critical, and may range from 4.7k to 10k.

It is assumed that the minimum recommended configuration of 512 kilobyte of SRAM

and 32 kbytes of EPROM are used. A typical implementation would use four 128k x 8-

bit 15 ns SRAM, together with a 256 kbit (32k x 8-bit) 150 ns EPROM. Larger memories

may also be used if more buffer space or MAC addresses are to be supported; if this is

done, the configuration parameters in the EPROM must be changed to reflect the

increased memory size. The SRAM and EPROM device types and speeds are defined

by the setting of the pull-up / pull-down resistors on the memory data bus during reset

time.

The power-on reset generator can be created either from discrete components, or from

a low-cost CPU monitor; the ERST* output from the ELAN 1x100 chip is strapped to the

reset signal to implement the watchdog capability of the ELAN device. Note that the

ERST* output may, as an alternative, used to signal some external processor that the

ELAN 1x100 device has encountered a fatal error condition requiring a software or

hardware reset; in this case, the ERST* output should be pulled up using a 2.7k

resistor.

The LED register is implemented using a simple 8-bit TTL register with a clock enable

that is tied to the indicated chip select output from the ELAN 1x100. Eight LEDs may be

connected to the outputs of this register to present the diagnostic status codes output

by the ELAN 1x100 firmware during self-test, system boot and operation. If a simple

TTL register is used, the LED register is effectively write-only; writes to this register will

modify the state of the LEDs, but reads from this register return invalid values. A read-

back register can be used if this is a significant issue.

The first three chip select lines from the ELAN 1x100 (i.e., MCS[0]*, MCS[1]* and

MCS[2]*) are tied to the SRAM, the EPROM and the LED register, respectively; the

remaining chip select is unused. This maps the SRAM into the first bank of address

space, the EPROM into the second bank, and the LED register into the third bank. The

address map in the following subsection gives the 24-bit address ranges assigned to

each resource.

This system has only been presented to serve as a basis for the following discussion on

the device and system operation, and is not intended to serve as a complete example

or reference design. More details on actual system construction with the ELAN 1x100

may be found in the relevant application notes and reference design documents.

System Memory Map

The ELAN 1x100 device uses a single linear (flat) byte-addressable 16 MB address

space for accessing memory and memory-mapped devices. The external memory map

for the system described above is quite straightforward. From the point of view of the

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