PM3351-SW datasheet(63/268 Pages) PMC

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PM3351 ELAN 1X100

DATA SHEET

PMC-970113

ISSUE 3

SINGLE PORT FAST ETHERNET SWITCH

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE

MDATA[30]

RISCRUN

A low on this signal halts the Switch Processor upon reset,

effectively placing the device into stand-by mode.

MDATA[29]

RSTTM

For test purposes only. Pull low for correct operation.

MDATA[28]

IMDIS

Internal memory disable: if high, the internal Switch Processor

ROM is disabled at initialization time.

MDATA[27]

PCI3V

If high, configures the PCI interface for the 3.3V signaling

environment. If low, configures the PCI interface for the 5V

signaling environment. Must be set to logic 0 since all AC

parametric testing done with the 5V signaling conditions.

MDATA[26]

FIRM

Reserved for use by Switch Processor firmware.

MDATA[25:22]

CHIPID[3:0]

These bits determine the PCI memory base address at

initialization time if the PCIRUN configuration bit is high. In this

case, the CHIPID[3:0] inputs are zero-extended to 8 bits and

loaded into the most significant byte of the Memory Base

Address register in the PCI configuration register space.

MDATA[21:16]

RTCDIV[5:0]

Real time clock divider: selects the divide ratio used for the

internal real-time clock prescaler. This field must be set

numerically equal to the frequency, in megahertz, of the clock

supplied on the SYSCLK input.

MDATA[15:14]

MXSEL[1:0]

Error! No index entries found.

MXSEL

Column Address

Bits

DRAM Configurations

Supported

64K x N & 128K x N

256K x N & 512K x N

1024K x N & 2048K x N

4 Meg x N & 8 Meg x N

MDATA[13]

MSLO

The MSLO bit extends read and write cycles to accommodate

slower DRAM devices in local memory devices. If MSLO is

high, 80ns DRAM is expected. If MSLO is low, 60ns DRAM is

expected. (MSLO must be a logic 0 if EDO DRAM is used with

the PM3351 since the device is intended to work with 60 ns

DRAM; as previously stated, DRAM, if used, is intended for non-

switching applications).

MDATA[12]

MDCAS

This bit identifies the type of DRAM connected to the memory

interface. If MDCAS is high, the memory interface will generate

control signals for 2-CAS DRAMs; otherwise, it generates

signals for single CAS DRAMs. (Again, as DRAM is generally

not used for standard switching, these bits will usually be don’t-

cares).

MDATA[11:9]

MTYPE3[2:0]

Indicates the type of memory connected to the MCS[3]* output:

MTYPE3[2:0]

000

001

010

011

100

101

110

111

Selected memory type

Reserved

15ns SRAM

Reserved

150ns (E)EPROM

60ns EDO DRAM

Reserved

PM3351-SW Datasheet(PDF) 63 Page - PMC-Sierra, Inc

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