PM3351-SW datasheet(53/268 Pages) PMC

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PM3351 ELAN 1X100

DATA SHEET

PMC-970113

ISSUE 3

SINGLE PORT FAST ETHERNET SWITCH

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE

Multichannel DMA Controller

The on-chip DMA Controller contains four independent and concurrently operating

channels: two for the 100 Mbit/s MII port (one for receive and one for transmit) and two

dedicated to the 1 Gbit/s expansion port. The DMA Controller, operating under the

control of the switch processor, is responsible for performing all data block transfers

within the ELAN 1x100 made between the MII port, the local memory and the

expansion port. The DMA Controller also computes 32-bit IEEE Frame Check

Sequence (FCS) remainders over the received and transmitted frames, allowing the

Switch Processor to filter frames with CRC errors on receive, and also allowing CRCs to

be computed for injected management frames on transmit. In addition, the DMA

Controller implements an address lookup process that attempts to map the 48-bit MAC

addresses of received frames to entries in an address table maintained in local

memory. The DMA Controller provides sufficient bandwidth to guarantee that there will

be continuous and uninterrupted reception and transmission of frames at full wire rates.

A special feature of the DMA Controller is its ability to automatically allocate buffer

storage from a central free pool (organized as a linked-list pointed to by a dedicated

device register) These allocatable data structures are called

packet buffers; they are of

fixed (and configurable) length, and are chained together into linked-lists to hold

Ethernet frames of different lengths. The DMA channel associated with the receive path

is capable of creating these linked-lists of packet buffers automatically whenever

frames are received.

The four DMA Controller channels are dedicated to various functions as follows:

•

One channel (referred to as the receive channel) is used to perform data

transfers between the MAC receive FIFO and the local memory, copying

received frame data from the FIFO to the local memory. As mentioned, the

receive channel generates a linked-list of packet buffers in external memory,

automatically allocating packet buffers as needed from a central free pool. A

32-bit CRC is computed on the receive data transfers, and the CRC result is

accessible to the Switch Processor firmware in the form of a CRC error status

bit after a frame has been received.

•

One channel (referred to as the transmit channel) is used to perform block

transfers over the external PCI expansion bus from external devices (other

ELAN 1x100s, ELAN 8x10s, or any other device implementing the same

protocol) to the 2048-byte transmit FIFO. This channel can follow a chain of

remote source packet buffers, reading data over the PCI bus. Only the required

frame data is written into the transmit FIFO; the headers of the packet buffers

are stripped off by the channel transfer logic.

The transmit channel implements special logic that allows the Switch Processor to

inspect the frame header and determine how the frame should be treated after it has

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