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PM3351-SW Datasheet(PDF) 74 Page - PMC-Sierra, Inc |
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PM3351-SW Datasheet(HTML) 74 Page - PMC-Sierra, Inc |
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74 / 268 page  PM3351 ELAN 1X100 DATA SHEET PMC-970113 ISSUE 3 SINGLE PORT FAST ETHERNET SWITCH PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 68 The codes written out to the LED register are defined below: Description LED7 LED6 LED5 LED4 LED3 LED2 LED1 LED0 Bootstrap Tag Index Off Off Off Tag[4] Tag[3] Tag[2] Tag[1] Tag[0] Operational Status Indication Off Off On Info[4] Info[3] Info[2] Info[1] Info[0] Boot Checksum Failure Blinking On Off Off Off Off Off On RAM Self-test Failure Blinking On Off Off Off Off On Off Operational Failure Blinking On On Code[4] Code[3] Code[2] Code[1] Code[0] If a failure is detected at any time that causes the ELAN 1x100 to halt normal operation, the most significant LED (connected to bit 7 of the LED register) will be made to blink on and off at a 0.5 second rate. The next-most-significant LED (i.e., bit 6 of the LED register) will be turned ON by writing a zero to this bit position of the LED register; this serves as a global failure indication, and may alternatively be polled by system hardware to determine whether a failure has occurred. LED number 5 indicates whether the failure occurred during system boot-up or normal operation: if it is lit, the system encountered an unrecoverable error during operation. The remaining five LEDs are used to signal an error-specific code that can be used for diagnostic purposes. The codes signalling tag processing information, operational information and operational errors during operation are TBD. Data Structures It is assumed that an earlier bootstrap initialization and configuration phase will have set up some predefined data structures in ELAN 1x100 local memory. These are the Switch Processor operating environment (stacks, memory pool, local variables, etc.), Transfer rings, free pools (containing Packet Buffers, Data Descriptors for messages, Hash Buckets and Forwarding Tags), the Port Descriptor Table (with the associated per-port section of the Management Information Base), the MAC address hash table (which also contains the per-host section of the Management Information Base), and data associated with the IEEE 802.1d spanning tree bridge configuration algorithm. The data structures, their function, and the operations performed on them are described below. In addition, the memory requirements for each type of structure, as well as the general memory map expected by the Switch Processor operating firmware, are provided in this section. The general layout of the various data structures in RAM is shown below. Note that addresses increase downwards. The actual addresses delimiting various regions of memory are implementation-specific, and not provided here; instead, the names of the |
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