PM5366 datasheet(173/267 Pages) PMC

173 / 267 page

PRELIMINARY

PM5366 TEMAP-84

DATASHEET

PMC-2010672

ISSUE 1

HIGH DENSITY 84/63 CHANNEL VT/TU MAPPER

AND M13 MULTIPLEXER

PROPRIETARY AND CONFIDENTIAL

161

accessed (with respect to WRB rising edge and RDB falling edge) at a rate no

faster than 1/8 that of the DS3 or E3 clock. This time is used by the high-speed

system clock to sample the event, write the FIFO, and update the FIFO status.

Instantaneous variations in the high-speed reference clock frequencies (e.g. jitter

in the line clock) must be considered when determining the procedure used to

read and write the TDPR registers.

Upon reset of the TEMAP-84, the TDPR should be disabled by setting the EN bit

in the TDPR Configuration Register to logic 0 (default value). An HDLC all-ones

Idle signal will be sent while in this state. The TDPR is enabled by setting the EN

bit to logic 1. The FIFOCLR bit should be set and then cleared to initialize the

TDPR FIFO. The TDPR is now ready to transmit.

To initialize the TDPR, the TDPR Configuration Register must be properly set. If

FCS generation is desired, the CRC bit should be set to logic 1. If the block is to

be used in interrupt driven mode, then interrupts should be enabled by setting

the FULLE, OVRE, UDRE, and LFILLE bits in the TDPR Interrupt Enable register

to logic 1. The TDPR operating parameters in the TDPR Upper Transmit

Threshold and TDPR Lower Interrupt Threshold registers should be set to the

desired values. The TDPR Upper Transmit Threshold sets the value at which the

TDPR automatically begins the transmission of HDLC packets, even if no

complete packets are in the FIFO. Transmission will continue until the current

packet is transmitted and the number of bytes in the TDPR FIFO falls to, or

below, this threshold level. The TDPR will always transmit all complete HDLC

packets (packets with EOM attached) in its FIFO. Finally, the TDPR can be

enabled by setting the EN bit to logic 1. If no message is sent after the EN bit is

set to logic 1, continuous flags will be sent.

The TDPR can be used in a polled or interrupt driven mode for the transfer of

data. In the polled mode the processor controlling the TDPR must periodically

read the TDPR Interrupt Status register to determine when to write to the TDPR

Transmit Data register. In the interrupt driven mode, the processor controlling

the TDPR uses the INTB output, the one of the TEMAP-84 Master Interrupt

Source registers, and the TEMAP-84 TDPR Interrupt Status registers to identify

TDPR interrupts which determine when writes can or must be done to the TDPR

Transmit Data register.

Interrupt Driven Mode:

The TDPR automatically transmits a packet once it is completely written into the

TDPR FIFO. The TDPR also begins transmission of bytes once the FIFO level

exceeds the programmable Upper Transmit Threshold. The CRC bit can be set

to logic 1 so that the FCS is generated and inserted at the end of a packet. The

TDPR Lower Interrupt Threshold should be set to such a value that sufficient

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