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PM7340 Datasheet(PDF) 39 Page - PMC-Sierra, Inc

Part # PM7340
Description  S/UNI INVERSE MULTIPLEXING FOR ATM, 8 LINKS
PDF  334 Pages
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Manufacturer  PMC [PMC-Sierra, Inc]
Direct Link  http://www.pmc-sierra.com
Logo PMC - PMC-Sierra, Inc

PM7340 Datasheet(HTML) 39 Page - PMC-Sierra, Inc

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PRELIMINARY
INVERSE MULTIPLEXING OVER ATM
PM7340 S/UNI-IMA-8
DATA SHEET
PMC-2001723
ISSUE 3
INVERSE MULTIPLEXING OVER ATM
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
22
Pin Name
Type
Pin
No.
Function
TADR[6]
TADR[5]
TADR[4]
TADR[3]
TADR[2]
TADR[1]
TADR[0]
Input
K19
K22
K21
K20
J19
J22
J21
The Transmit Address (TADR[6:0]) signals are
used to address logical channels for the purpose of
polling and device selection. The TADR[6:0] signals
are valid only when the TCSB signal is sampled
active in the following TCLK cycle.
The TADR[6:0] input bus is sampled on the rising
edge of TCLK.
TCSB
Input
J20
The Transmit Chip Select (TCSB) is an active low
signal that is used to select the S/UNI-IMA-8
transmit interface. When the TCSB is sampled low, it
indicates that the TADR[6:0] sampled at the
previous clock is a valid address. If the TCSB is
sampled high, the device is not selected and the
TADR[6:0] sampled on the previous cycle is not a
valid address and is ignored. When sufficient
address space is provided by TADR[6:0] for all
devices on the bus, this signal may be tied low.
The TCSB is asserted low one cycle after a valid
address is present on the TADR[6:0] signals.
The TCSB input is sampled on the rising edge of
TCLK.
TSOP
Input
H19 The Transmit Start of Packet (TSOP) is an active
high signal that marks the start of the cell on the
TDAT[15:0] bus. When TSOP is active, the first word
of the cell is present on the TDAT[15:0] bus.
The TSOP output is sampled on the rising edge of
TCLK.
TSX
Input
H22 The Transmit Start of Transfer (TSX) signal is an
active high signal that marks the first cycle of a data-
block transfer on the TDAT[15:0] bus. When the
TSX signal is active, the coinciding data on the
TDAT[15:0] bus represents the in-band PHY
address.
The TSX output is sampled on the rising edge of
RCLK.



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