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S/UNI®-JET Data Sheet

Released

Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use

Document ID: PMC-1990267, Issue 3

Description

The PM7346 S/UNI-JET is an ATM physical layer processor with integrated DS3, E3, and J2

framers. It supports PLCP sublayer DS1, DS3, E1, and E3 processing and ATM cell delineation.

The S/UNI-JET contains:

• An Integral DS3 framer that provides DS3 framing and error accumulation in accordance

with ANSI T1.107, and T1.107a.

• An Integral E3 framer that provide E3 framing in accordance with ITU-T Recommendations

G.832 and G.751.

• An Integral J2 framer that provide J2 framing in accordance with ITU-T Recommendation

G.704 and I.432.

When configured for various transmission system sublayer processing, the S/UNI-JET accepts

and outputs the appropriate type of bipolar and unipolar signals as described in Table 2:

Table 2 Transmission System Sublayer Processing Acceptance and Output

Transmission System

Sublayer Processing

Acceptance and Output

DS3

Accepts and outputs both digital B3ZS-encoded bipolar and unipolar

signals compatible with M23 and C-bit parity applications.

Accepts and outputs both HDB3-encoded bipolar and unipolar signals

compatible with G.751 and G.832 applications.

Accepts and outputs both B8ZS-encoded bipolar and unipolar signals

compliant with G.704 and NTT 6.312 Mbit/s applications.

DS1, or E1

Accepts and outputs outputs unipolar signals with appropriate clock and

frame pulse signals for physical sublayer processing.

Other transmission systems

Provides a generic interface for physical sublayer processing.

In the DS3 receive direction, the S/UNI-JET frames to DS3 signals with a maximum average

reframe time of 1.5 ms and detects line code violations (LCV), loss of signal (LOS), framing bit

errors, parity errors, path parity errors, alarm indication signals (AIS), far end receive failure

(FERF), and idle code. The DS3 overhead bits are extracted and presented on serial outputs.

When in C-bit parity mode, the Path Maintenance Data Link (PMDL) and the Far End Alarm and

Control (FEAC) channels are extracted. HDLC receivers are provided for PMDL support. Valid

bit-oriented codes in the FEAC channels are also detected and are available through the

microprocessor port.

Table 3 Summary of Receive Detection Features

Transmission System

Sublayer Processing

Transmit or

Receive

Detected Features

DS3

Receive

LCV, LOS, framing bit errors, parity errors, path parity

errors, AIS, FERF, and idle code

Receive

LCV, LOS, framing bit errors, AIS, and RAI

PM7347 Datasheet(PDF) 29 Page - PMC-Sierra, Inc

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