PM7347 datasheet(36/341 Pages) PMC

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S/UNI®-JET Data Sheet

Released

Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use

Document ID: PMC-1990267, Issue 3

Pin Name

Type

No.

Function

RNEG

RLCV

ROHM

Input

The Receive Digital Negative Pulse (RNEG) contains the

negative pulses received on the B3ZS encoded DS3, the

HDB3-encoded E3, or the B8ZS-encoded J2

transmission system when the dual-rail NRZ input format

is selected.

The Receive LCV (RLCV) contains LCV indications when

the single-rail (unipolar) NRZ input format is enabled for

DS3, E3, or J2 applications. Each LCV is represented by

an RCLK period-wide pulse.

When a DS1 or E1 PLCP or ATM direct-mapped signal is

received, Receive Overhead Mask (ROHM) is pulsed

once per transmission frame, and indicates the DS1 or

E1 frame alignment relative to the RDATI data stream.

When an alternate frame-based signal is received,

ROHM indicates the position of each overhead bit in the

transmission frame.

The RNEG/RLCV/ROHM pin function selection is

controlled by the RFRM[1:0] bits in the S/UNI-JET

Receive Configuration Register, the UNI bits in the DS3

FRMR, E3 FRMR, or J2 FRMR Configuration Register,

and the PLCPEN and EXT bits in the SPLR

Configuration Register.

RNEG, RLCV, and ROHM are sampled on the rising

edge of RCLK by default, and may be enabled to be

sampled on the falling edge of RCLK. This sampling is

controlled by the RCLKINV bit in the S/UNI-JET Receive

Configuration Register.

Note: Signal polarity control is provided by the RNEGINV

bit in the S/UNI-JET Receive Configuration Register.

RCLK

Input

The Receive Clock (RCLK) provides the receive direction

timing. RCLK is the externally recovered transmission

system baud rate clock that samples the RPOS/RDATI

and RNEG/RLCV/ROHM inputs on its rising or falling

edge.

TOHINS

Input

The Transmit DS3/E3/J2 Overhead Insertion (TOHINS)

controls the insertion of the DS3, E3, or J2 overhead bits

from the TOH input.

When TOHINS is high, the associated overhead bit in the

TOH stream is inserted in the transmitted DS3, E3, or J2

frame. When TOHINS is low, the DS3, E3, or J2

overhead bit is generated and inserted internally.

TOHINS is sampled on the rising edge of TOHCLK. If

TOHINS is a logic one, the TOH input has precedence

over the internal datalink transmitter, or any internal

PM7347 Datasheet(PDF) 36 Page - PMC-Sierra, Inc

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