PM7347 datasheet(48/341 Pages) PMC

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S/UNI®-JET Data Sheet

Released

Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use

Document ID: PMC-1990267, Issue 3

Pin Name

Type

No.

Function

RCA

Output

N19

The Receive Multi-PHY Cell Available (RCA) signal

indicates when a cell is available in the receive FIFO for

the device selected by RADR[2:0].

RCA can be configured to be de-asserted when either

zero or four bytes remain in the selected/addressed

FIFO. RCA will thus transition low on the rising edge of

RFCLK after Payload byte 48 (RCALEVEL0=1) or 43

(RCALEVEL0=0) is output for the 8-bit interface

(ATM8=1), or after Payload word 24 (RCALEVEL0=1) or

19 (RCALEVEL0=0) is output for the 16-bit interface

(ATM8=0) if the PHY being polled is the same as the

selected device.

RCA is tri-stated when either the null-PHY address (7H)

or an address not matching the address space set by

PHY_ADR[2:0] is latched (by RFCLK) from the

RADR[2:0] inputs.

The polarity of RCA (with respect to the description

above) is inverted when the RCAINV register bit is set to

logic one.

RFCLK

Input

P20

The Receive FIFO Read Clock (RFCLK) signal is used

to read ATM cells from the receive FIFOs. RFCLK must

cycle at a 52 MHz or lower instantaneous rate, but at a

high enough rate to avoid FIFO overflows.

DRCA

Output

L17

The Direct Access Receive Cell Available (DRCA) output

signals indicate when a cell is available in the receive

FIFO.

DRCA can be configured to be de-asserted when either

zero or four bytes remain in the FIFO. DRCA will thus

transition low on the rising edge of RFCLK after Payload

byte 48 (RCALEVEL0=1) or 43 (RCALEVEL0=0) is

output for the 8-bit interface (ATM8=1), or after Payload

word 24 (RCALEVEL0=1) or 19 (RCALEVEL0=0) is

output for the 16-bit interface (ATM8=0).

The DRCA outputs can be used to support Utopia Direct

Access mode.

PHY_ADR[2]

PHY_ADR[1]

PHY_ADR[0]

Input

K18

L20

L19

The Device Identification Address (PHY_ADR[2:0])

inputs represent the address space which this S/UNI-JET

occupies.

When the PHY_ADR[2:0] inputs match the TADR[2:0] or

RADR[2:0] inputs, then this S/UNI-JET is selected for

transmit or receive ATM access.

Note: The null-PHY address 7H is an invalid address and

will not select the S/UNI-JET. The S/UNI-JET can be

used directly in applications requiring 7 or fewer ports.

Applications requiring more than 7 ports may require

external decoding of the Utopia address to avoid bus

contention.

CSB

Input

The Active low Chip Select (CSB) signal must be low to

enable S/UNI-JET register accesses. If CSB is not used,

(RDB and WRB determine register reads and writes)

then it should be tied to an inverted version of RSTB.

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