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PM7347 Datasheet(PDF) 88 Page - PMC-Sierra, Inc

Part # PM7347
Description  SATURN USER NETWORK INTERFACE for J2/E3/T3
PDF  341 Pages
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Manufacturer  PMC [PMC-Sierra, Inc]
Direct Link  http://www.pmc-sierra.com
Logo PMC - PMC-Sierra, Inc

PM7347 Datasheet(HTML) 88 Page - PMC-Sierra, Inc

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S/UNI®-JET Data Sheet
Released
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
88
Document ID: PMC-1990267, Issue 3
TICLK
The TICLK bit selects the transmit clock used to update the TPOS/TDATO and
TNEG/TOHM outputs. When a logic zero is written to TICLK, the buffered version of the
input transmit clock, TCLK, is used to update TPOS/TDATO and TNEG/TOHM on the edge
selected by the TCLKINV bit. When a logic one is written to TICLK, TPOS/TDATO and
TNEG/TOHM are updated on the rising edge of TICLK, eliminating the flow-through TCLK
signal. The TICLK bit has no effect if the LOOPT, LLOOP, or PLOOP bit is a logic one.
TXREF
The TXREF register bit determines if TICLK[1] and TIOHM/TFPI/TMFPI[1] should be used
as the reference transmit clock and overhead/frame pulse, respectively, instead of TICLK and
TIOHM/TFPI/TMFPI. If TXREF is set to a logic one, then TICLK[1] and
TIOHM/TFPI/TMFPI[1] will be used as the reference transmit clock and overhead/frame
pulse, respectively. If TXREF is set to a logic zero, then TICLK and TIOHM/TFPI/TMFPI
will be used as the reference transmit clock and overhead/frame pulse, respectively, for
quadrant X. If loop-timing is enabled (LOOPT = 1), the TXREF bit has no effect on the
corresponding quadrant. Note: When TXREF is set to logic one, the unused TICLK and
TIOHM/TFPI/TMFPI should be tied to power or ground, not left floating.
TFRM[1:0]
The TFRM[1:0] bits determine the frame structure of the transmitted signal. Refer to Table 8:
Table 8 TFRM[1:0] Transmit Frame Structure Configurations
TFRM[1:0]
Transmit Frame Structure
00
DS3 (C-bit parity or M23 depending on the setting of the CBIT bit in the DS3
TRAN Configuration Register)
01
E3 (G.751 or G.832 depending on the setting of the FORMAT[1:0] bits in the
E3 TRAN Framing Options Register)
10
J2 (G.704 and NTT compliant framing format)
11
DS1/E1/Arbitrary framing format - If the EXT bit in the SPLT Configuration
Register is a logic zero, then DS1 or E1 direct-mapped or PLCP framing is
selected (via the PLCPEN and FORM[1:0] bits in the SPLT Configuration
Register) and TIOHM should be tied low. If EXT is a logic one, then the
arbitrary framing format is selected and overhead positions are indicated by
the TIOHM input pin.



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