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S/UNI®-JET Data Sheet

Released

Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use

Document ID: PMC-1990267, Issue 3

The S/UNI-JET provides cell delineation for ATM cells using the PLCP framing format, or by

using the header check sequence octet in the ATM cell header as specified by ITU-T

Recommendation I.432. DS1, DS3, E1, and E3-based PLCP frame formats can be processed.

Non-PLCP-based cell delineation is done with either bit, nibble, or byte-wide search algorithms

depending on the line interface used. An interface consistent with the generic physical interface

defined by ITU-T Recommendation I.432 is provided for arbitrary rates up to 52 Mbit/s. This

interface is used for PHY layer support for transmission systems that do not have an associated

PLCP sublayer, or to provide an efficient means of directly mapping ATM cells to existing

transmission system formats (such as DS3 and DS1).

In the PLCP receive direction, framing, path overhead extraction, and cell extraction is provided.

BIP-8 error events, frame octet error events, and FEBE events are accumulated.

In the PLCP transmit direction, the S/UNI-JET provides overhead insertion using inputs or

internal registers, DS3 nibble and E3 byte stuffing, automatic BIP-8 octet generation and

insertion, and automatic FEBE insertion. Diagnostic features for BIP-8 error, framing error and

FEBE insertion are also supported.

In the cell receive path, idle cells may be dropped according to a programmable filter. By default,

incoming cells with single bit HCS errors are corrected and written to the FIFO buffer.

Optionally, cells can be dropped upon detection of a HCS error. Cell delineation may optionally

be disabled to allow all cells to pass, regardless of cell delineation status. The ATM cell payloads

are optionally descrambled. ATM cell headers may optionally be descrambled (for use with PPP

packets). Assigned cells containing no detectable HCS errors are written to a FIFO buffer. Cell

data is read from the FIFO using a synchronous 50 MHz 8-bit wide or 16-bit wide SCI-PHY

and Utopia Level 2-compatible interface. Cell data parity is also provided. Counts of error-free

assigned cells, and cells containing HCS errors are accumulated independently for performance

monitoring purposes.

In the cell transmit path, cell data is written to a FIFO buffer using a synchronous 50 MHz 8-bit

wide or 16-bit wide SCI-PHYTM compatible interface. Cell data parity is also examined for errors.

Idle cells are automatically inserted when the FIFO contains less than one full cell. HCS

generation, cell payload scrambling, and cell header scrambling (for use with PPP packets) are

optionally provided. Counts of transmitted cells are accumulated for performance monitoring

purposes.

Both receive and transmit cell FIFOs provide buffering for four cells. The FIFOs provide the rate

matching interface between the higher layer ATM entity and the S/UNI-JET.

The S/UNI-JET is configured, controlled, and monitored by a generic 8-bit microprocessor bus

through which all internal registers are accessed. All sources of interrupts can be identified,

acknowledged, or masked with this interface.

The S/UNI-JET requires a software initialization sequence in order to guarantee proper device

operation and long term reliability. Please refer to Section 13.1 of this document for the details on

how to program this sequence.

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