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405EZ Datasheet(PDF) 5 Page - Applied Micro Circuits Corporation |
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405EZ Datasheet(HTML) 5 Page - Applied Micro Circuits Corporation |
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5 / 54 page ![]() PPC405EZ – PowerPC 405EZ Embedded Processor Revision 1.27 - August 22, 2007 AMCC Proprietary 5 Preliminary Data Sheet Block Diagram Figure 1. PPC405EZ Embedded Controller Functional Block Diagram The PPC405EZ is designed using the IBM Microelectronics Blue LogicTM methodology in which major functional blocks are integrated together to create an application-specific ASIC product. This approach provides a consistent way to create complex ASICs using IBM CoreConnectTM Bus Architecture. D-OCM I-OCM 32KB SRAM DCR GPIO IIC/ Timer/ MAL Ethernet DMA Bridges Clock Control Reset Power Mgmt JTAG Trace Timers MMU MII Controller OPB/PLB Interrupt Controller Arbiter Universal (4-Channel) DCRs Arbiter UART x2 CAN x2 SPI USB 1.1 Host/Dev NAND Flash Controller (SCP) DAC ADC OCM Ctrl 16KB I-Cache 16KB D-Cache On-chip Peripheral Bus (OPB) Processor Local Bus (PLB) 64 bit, PLB3 PowerPC 405 Core IEEE External Bus Controller 10/100 1588 Bus BSC PWM PTP PHY |
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