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TMPR4956C Datasheet(PDF) 202 Page - Toshiba Semiconductor

Part # TMPR4956C
Description  64-Bit TX System RISC TX49 Family
PDF  286 Pages
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Manufacturer  TOSHIBA [Toshiba Semiconductor]
Direct Link  http://www.semicon.toshiba.co.jp/eng
Logo TOSHIBA - Toshiba Semiconductor

TMPR4956C Datasheet(HTML) 202 Page - Toshiba Semiconductor

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Chapter 11 TX4956 System Interface
11-34
11.3 System Interface of R4300 Type Protocol Mode
Note: This mode is available for TX4956 with 32-bit bus width
In TX4956, it is built in system interface function corresponding to R4300 type protocol. A selection of
above-mentioned R5000 type protocol mode or R4300 type protocol mode increases by external pin
(MODE43* :Pin No. B15).
The R4300 type protocol mode setting is as follows:
BSIZE64*=0
MODE43* = 0
Note:
In R4300 type protocol mode of TX4956, there is not PReq output signal. Therefore PReq
input signal of an external agent should be always fixed in “Low”. And also there is not a
function to show that protocol errors were detected. Otherwise, TX4956 has a built-in counter,
and when there is no reply detected to read request in a certain time, bus error exception
occurs.
11.3.1
System Interface Description of R4300 Type Protocol Mode
The TX4956 processor has a 32-bit address/data interface. The System interface consists of:
•
32-bit address and data bus, SysAD
•
5-bit command bus, SysCmd
•
five handshake signals:
– EValid*, PValid*
– EReq*
– PMaster*, EOK*
Table 11.3.1 System Interface Signals (When R4300 type protocol mode (MODE43* = 0, BSIZE64*=0))
Signal Name
Pin No.
I/O
Function
SysAD[63:32]
B5, B6, B7,
B8, B9, B10,
B11, B12,
B13, B14,
E14, F14,
G14, H14,
J14, K14,
L14, M14,
N14, P14,
P13, P4, P3,
N2, M2, L2,
K2, J2, E2,
D2, C2, B2
I/O
Reserved
These pins are always driven to 0, then, can be left open on the board
SysAD[31:0]
A10, A11,
A12, A13,
C15, D15,
E15, F15,
G15, H15,
J15, K15,
L15, M15,
N15, P15,
L1, K1, J1,
H2, H1, G2,
G1, F2, F1,
E1, D1, C1,
A6, A7, A8,
A9
I/O
System address/data bus
A 32-bit address and data bus for communication between the processor and an
external agent.



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