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TMPR4956C Datasheet(PDF) 200 Page - Toshiba Semiconductor

Part # TMPR4956C
Description  64-Bit TX System RISC TX49 Family
PDF  286 Pages
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Manufacturer  TOSHIBA [Toshiba Semiconductor]
Direct Link  http://www.semicon.toshiba.co.jp/eng
Logo TOSHIBA - Toshiba Semiconductor

TMPR4956C Datasheet(HTML) 200 Page - Toshiba Semiconductor

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Chapter 11 TX4956 System Interface
11-32
11.2.12 System Interface Addresses
11.2.12.1 Addressing rules
Addresses that are to be used in word or partial word transactions are arranged to match the size
of the data element. The following rules are used by this system.
•
Target addresses of the block request are aligned to the word boundaries. In other words,
the lower 2 bits of the address become 0.
•
Word requests set the lower 2 bits of the address to 0.
•
Half-word requests set the least significant bit of the address to 0.
•
Byte requests and 3-byte requests use the byte address.
11.2.13 Mode Register of System Interface (G2SConfig)
The Mode Register of System Interface (G2SConfig) is a read/write register. This register is used to
specify a protocol type of a processor write request etc. This register is only Word-Access.
Table 11.2.17 G2SConfig
Address
Field Name
Description
0xF_FF10_0000
G2SConfig
Mode Register of System Interface
31
20
19
4
3
2
1
0
Bit
Reserved
Reserved
Reserved
Write mode
Data rate
Bit(s)
Field Name
Description
Cold Reset
Read/Write
31:20
Reserved
Read as undefined. Must be written as 0xfff.
Undefined
Read
19:4
Reserved
Read as undefined. Must be written as 0xffff.
0xffff
Read/Write
3
Reserved
Read as undefined. Must be written as 0.
0
Read/Write
2:1
Write mode
Processor single write protocols set
00: R4000 compatible write
01: Reserved
10: Pipeline write
11: Reissue write
00
Read/Write
0
Data rate
Data transfer rate set for the block write
when 64-bit bus width
0: DDDD
1: DxxDxxDxxDxx
when 32-bit bus width
0 : WWWWWWWW
1: WxxWxxWxxWxxWxxWxxWxxWxx
0
Read/Write
Note:
When initialized Single write: when 64-bit bus width
ADxx,
when 32-bit bus width
AWxx (R4000 compatible)
Block write: when 64-bit bus width
ADDDD,
when 32-bit bus width
AWWWWWWWW
Figure 11.2.29 G2SConfig Register Formats(When R5000 protocol (MODE*=1))



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