TMPR4956C datasheet(217/286 Pages) TOSHIBA

217 / 286 page

Chapter 11 TX4956 System Interface

11-49

For 1-to 4-byte writes, a single data cycle is used. 5-, 6- and 7-byte writes are broken up into two

address/data transactions; one 4 bytes in size, the next handling the remaining 1, 2, or 3 bytes.

More than 8 bytes (e.g. 8, 16, 32), 4 bytes are sent on each data cycle until the appropriate number of bytes

has been transferred. The final data cycle is tagged as end of data (EOD) on the command bus.

To be fully compliant with all implementations of this protocol, an external agent should be able to

receive write data over any number of cycles with any number of idle cycles between any two data cycles.

However, for the TX4956 processor implementation, data begins to arrive on the cycle immediately

following the write issue cycle, and continues to arrive at a programmed data rate thereafter. The

processor drives data at the rate specified by the data rate configuration signals (see the section describing

Data Rate Control, later in this chapter).

Writes may be cancelled and retried with the EOK* signal (see the section earlier, Issuing Commands).

Figure 11.3.14 illustrates the bus transactions for a 4-word data cache block store.

Figure 11.3.14 Processor Block Write Request With W Data Rate

Figure 11.3.15 illustrates a write request which is cancelled by the deassertion of EOK* during the

address cycle of the second write, and which is retried when EOK* is asserted again.

Figure 11.3.15 Processor Single Write Request Followed By A Cancelled And Retried Write Request

Data 0

Data

Write

Data

EOD

Data 3

Data 2

Data 1

Addr

SysAD

Cycle

MasterClock

SysCmd

EOK*

PValid*

PMaster*

Data 0

Write

EOD

Data 1

Addr 1

Addr 0

SysAD

Cycle

MasterClock

SysCmd

EOK*

PValid*

PMaster*

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