TMPR4956C datasheet(235/286 Pages) TOSHIBA

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Chapter 12 TX4956 Processor Interrupts

12-3

12.5 Timer Interrupt

When the Timer Interrupt occurs, the bit 15 of Cause register is set to 1, which is bit 7 of the interrupt

pending, IP, filed in the Cause register.

Bit5 of the Interrupt register (means SysAD[5] pin) is ORed with the current value of the external interrupt

pin Int[5]*. When TintDis is asserted (High), this ORed signal is selected. And when TintDis is deasserted

(Low), then the Timer Interrupt is selected. The result is set to bit 15 of the Cause Register (IP7).

12.6 Masking of the TX4956 Interrupts

Figure 12.1.1 also shows the masking of the processor interrupt signals.

Bits 15-8 of the Cause register (IP7-IP0) are AND-ORed with Bits 15-8 of the Status register (IM7-IM0) to

mask individual interrupts.

Bit 0 of the Status register (IE) is a global Interrupt Enable. It is ANDed with the output of the AND-OR

logic to produce the processor interrupt signal. Bit 1 and 2 of the Status register (EXL and ERL) also enable

these interrupts.

12.7 Recognition of the Processor Interrupts

The results of the processor interrupts directly readable as bits 15-8 of the Cause register.

If any interrupts are occurred, the processor software needs to read the Cause register to recognize what type

of interrupts is occurred.

TMPR4956C Datasheet(PDF) 235 Page - Toshiba Semiconductor