TMPR4956C datasheet(237/286 Pages) TOSHIBA

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Chapter 13 Power-Saving Modes

13-1

13. Power-Saving Modes

The TX4956 has these power-saving modes:

•

Halt mode

•

Doze mode

The TX4956 enters neither Halt nor Doze mode by just programming the Config register. The WAIT instruction

puts the TX4956 in Halt or Doze mode.

13.1 Halt Mode

The Halt mode reduces power consumption by halting the TX4956 almost altogether. In Halt mode, the

internal clocks of the TX49/H4 core within the TX4956 are partially stopped. If the HALT bit in the Config

mode.

When the TX4956 enters Halt mode, the HALTDOZE signal is asserted. Even when an external agent has

ownership of the SysAD bus, executing the WAIT instruction puts the TX4956 in Halt mode, but the

HALTDOZE signal is asserted after the current bus cycle is completed. If the on-chip write buffer has any store

information, the WAIT instruction puts the TX4956 in Halt mode after it is emptied.

Assertion of Int[5:0]* signal, NMI* signal, ColdReset* signal or Reset* signal brings the TX4956 out of

Halt mode. The TX4956 recognizes the Int[5:0]* signal inputs, irrespective of the settings of the IntMask bits

in the Status register. On a return from Halt mode by NMI* signal, ColdReset* signal, Reset* signal or not

masked Int[5:0]* signals, the TX4956 takes a corresponding exception. At this time, the EPC register points to

the address of the instruction following the WAIT instruction. When the TX4956 is taken out of Halt mode as

the result of a masked Int[5:0]* signal, processing resumes from the instruction following the one that was

being executed when the TX4956 went into Halt mode.

13.2 Doze Mode

The Doze mode is also a software-controlled feature that reduces power consumption of the TX4956. In

Doze mode, the CPU pipeline status is retained and the internal clocks of the TX4956 are not stopped. If the

HALT bit in the Config register is set, executing the WAIT instruction causes the TX4956 to enter Doze mode.

When the TX4956 enters Doze mode, the HALTDOZE signal is asserted. Even when an external agent has

ownership of the SysAD bus, executing the WAIT instruction puts the TX4956 in Doze mode, but the

HALTDOZE signal is asserted after the current bus cycle is completed. If the on-chip write buffer has any store

information, the WAIT instruction puts the TX4956 in Doze mode after it is emptied.

Assertion of Int[5:0]* signal, NMI* signal, ColdReset* signal or Reset* signal brings the TX4956 out of

Doze mode. The TX4956 recognizes the Int[5:0]* signal inputs, irrespective of the settings of the IntMask bits

in the Status register. On a return from Doze mode by NMI* signal, ColdReset* signal, Reset* signal or not

masked Int[3:0]* signal, the TX4956 takes a corresponding exception. At this time, the EPC register points to

the address of the instruction following the WAIT instruction. When the TX4956 is taken out of Doze mode as

the result of a masked Int[5:0]* signal, processing resumes from the instruction following the one that was

being executed when the TX4956 went into Doze mode.

TMPR4956C Datasheet(PDF) 237 Page - Toshiba Semiconductor