TMPR4956C datasheet(239/286 Pages) TOSHIBA

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Chapter 14 JTAG Interface

14-1

14. JTAG Interface

The TX4956 processor provides a boundary-scan interface that is compatible with Joint Test Action Group

(JTAG) specifications, using the industry-standard JTAG protocol (IEEE Standard 1149.1/D6).

This chapter describes that interface, including descriptions of boundary scanning, the pins and signals used by

the interface, and the Test Access Port (TAP).

Note:

When performing a JTAG operation, be sure to run the MasterClock before and after a reset

operation to properly release the processor reset.

14.1 What Boundary Scanning Is

With the evolution of ever-denser integrated circuits (ICs), surface-mounted devices, double-sided

component mounting on printed-circuit boards (PCBs), and buried vias, in-circuit tests that depend upon

making physical contact with internal board and chip connections have become more and more difficult to use.

The greater complexity of ICs has also meant that tests to fully exercise these chips have become much larger

and more difficult to write.

One solution to this difficulty has been the development of boundary-scan circuits. A boundary-scan circuit

is a series of shift register cells placed between each pin and the internal circuitry of the IC to which the pin is

connected, as shown in Figure 14.1.1. Normally, these boundary-scan cells are bypassed; when the IC enters

test mode, however, the scan cells can be directed by the test program to pass data along the shift register path

and perform various diagnostic tests. To accomplish this, the tests use the four signals described in the next

section: JTDI, JTDO, JTMS, JTCK, and TRST*.

Figure 14.1.1 JTAG Boundary-scan Cells

Integrated Circuit

IC package pin

Boundary-scan cells

TMPR4956C Datasheet(PDF) 239 Page - Toshiba Semiconductor