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TMPR4956C Datasheet(PDF) 246 Page - Toshiba Semiconductor |
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TMPR4956C Datasheet(HTML) 246 Page - Toshiba Semiconductor |
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246 / 286 page  Chapter 14 JTAG Interface 14-8 14.3.8 TAP Controller The state transition diagram of the TAP controller is shown in Figure 14.3.8. Each arrow between states is labeled with a 1 or 0, indicating the logic value of JTMS that must be set up before the rising edge of JTCK to cause the transition. Figure 14.3.8 TAP Controller State Diagram The following paragraphs describe each of the controller state. The left vertical column in Figure 14.3.8 is the data column, and the right vertical column is the instruction column. The data column and instruction column reference data register (DR) and instruction register (IR), respectively. Test-Logic-Reset 1 0 0 1 0 1 Run-Test/Idle Select-DR-Scan 1 1 Capture-DR 0 Shift-DR 1 Exit 1-DR 0 Pause-DR 1 Exit 2-DR 1 Update-DR 0 1 0 0 1 Select-IR-Scan Capture-IR 0 Shift-IR 1 Exit 1-IR 0 Pause-IR 1 Exit 2-IR 1 Update-IR 0 1 1 00 1 0 0 0 |
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