ACT88320 datasheet(22/57 Pages) QORVO

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Data Sheet Rev. E, November 2019 | Subject to change without notice

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ACT88320

Advanced PMU with Inrush Control and Bypass Switch

Softstart Time. The softstart time is the time it takes an

output to ramp from 10% to 90% of its programmed

voltage. All buck converter softstart times are controlled

by a single I2C bit ALL_BUCKS_FASTER_SS. When

set to 0, the softstart times are 600µs. When set to 1,

the softstart times are 250µs. The default softstart time

can be changed after the IC is powered on, but it is

volatile and resets to the factory defaults when power is

recycled.

Output Voltage. The output voltage is each regulator’s

desired

voltage.

Each

buck’s

output

voltage

programmed via its I2C bits VSET0 and VSET1. The

output regulates to VSET0 in ACTIVE mode. They can

be programmed to regulate to VSET1 in DVS, SLEEP,

and DSPSLP modes. Each LDO has a single register,

VSET, to set its output voltage. Each output’s voltage

can be changed after the IC is powered on, but the new

setting is volatile and is reset to the factory defaults

when power is recycled. Output voltages can be

changed on the fly. If a large output voltage change is

required, it is best to make multiple smaller changes.

This prevents the IC from detecting an instantaneous

over or under voltage condition because the fault

thresholds are immediately changed, but the output

takes time to respond.

Dynamic Voltage Scaling

On-the-fly dynamic voltage scaling (DVS) for the three

buck converters is available via either the I2C interface

or a GPIO. DVS allows systems to save power by

quickly adjusting the microprocessor performance level

when the workload changes. Note that DVS is not a

different operating state. The IC operates in the ACTIVE

state, but just regulates the outputs to a different voltage.

Each buck converter operates at its VOUT0 voltage in

normal operation and operates at its VOUT1 voltage

when the DVS input trigger is active. DVS can be

implemented two ways.

DVS can be implemented for all buck converters at one

time via a single GPIO input. The IC’s specific CMI

determines the specific GPIO used for DVS. This setting

can be modified with a custom CMI.

DVS can be implemented for all buck converters at one

time via I2C. The user can select from two different

configurations to enter DVS via I2C. Note that DVS is

disabled when EN_DVS_I2C = 0.

Enable DVS via a single I2C write to

I2C_DVS_ON bit: With EN_DVS_I2C = 1

and SEL_DVS_IN = 0, the IC enters DVS

when I2C_DVS_ON = 1 and exits DVS

when it equals 0.

Enable DVS whenever the IC enters

SLEEP state: With EN_DVS_I2C = 1 and

SEL_DVS_IN = 1, any condition that puts

the IC into SLEEP state also puts the IC

into DVS mode. Note that I2C_DVS_ON bit

does not affect this configuration.

Note that the IC cannot be configured to enter DVS in

DPSLP state. Table 3 summarizes I2C DVS functionality.

EN_DVS_I2C

SEL_DVS_IN

I2C_DVS_ON

DVS

MODE

Off

On in

SLEEP

state

Table 3. I2C DVS Control

For fault free operation, the user must ensure output

load conditions plus the current required to charge the

output capacitance during a DVS rising voltage

condition does not exceed the current limit setting of the

regulator. As with any power supply, changing an output

voltage too fast can require a current higher than the

current limit setting. The user must ensure that the

voltage step, slew rate, and load current conditions do

not result in an instantaneous loading that results in a

current limit condition.

Input Voltage Monitoring (SYSMON)

The ACT88320 monitors the input voltage on the VIN

pins to ensure it is within specified limits for system level

operation.

The

“wakes

up”

and

allows

I2C

communication when VIN rises above UVLO (~2.7V).

However, the outputs do not turn on until VIN rises

above

the

SYSMON

threshold.

SYSMON

programmable between 2.7V and 4.2V. The IC then

asserts the nIRQ pin if VIN drops below SYSMON, but

the outputs continue to operate normally. The IC turns

off all outputs if the input voltage drops below UVLO. I2C

bit VSYSSTAT = 1 when VIN < SYSMON and 0 when

VIN > SYSMON. This fault can be masked with I2C bit

VSYSMSK.

Fault Protection

The ACT88320 contains several levels of fault

protection, including the following:

Output Overvoltage

Output Undervoltage

Output Current Limit and short circuit

Thermal Warning

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