ACT88320 datasheet(23/57 Pages) QORVO

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Data Sheet Rev. E, November 2019 | Subject to change without notice

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ACT88320

Advanced PMU with Inrush Control and Bypass Switch

Thermal Shutdown

There are three types of I2C register bits associated with

each fault condition: fault flag bits, fault bits, and mask

bits. The fault flag bits display the real-time fault status.

Their status is valid regardless of whether or not that

fault is masked. The mask bits either block or allow the

fault to affect the fault bit. Each potential fault condition

can be masked via I2C if desired. Any unmasked fault

condition results in the fault bit going high, which asserts

the nIRQ pin. nIRQ is typically active low. The nIRQ pin

only de-asserts after the fault condition is no longer

present and the corresponding fault bit is read via I2C.

Note that masked faults can still be read in the fault flag

bit. Refer to Active-Semi Application Note describing the

programming ranges.

nIRQ (Interrupt)

The interrupt function is typically used to drive the inter-

rupt input of the system processor. Many of the

ACT88320's functions support interrupt-generation as a

result of various conditions. These are typically masked

by default, but may be unmasked via the I2C interface.

For more information about the available fault condi-

tions, refer to the appropriate sections of this datasheet.

nIRQ can be triggered from:

Die temperature warning generated

Any buck regulator exceeding peak current limit

for 16 cycles after soft start or a UV/OV condi-

tion.

Any LDO regulator exceeding current limit for

more than 16uS after soft start or a UV/OV con-

dition.

Input goes above OVP threshold or falls below

the UV threshold.

If any of these faults occur the nIRQ output is asserted

active low. After nIRQ pin is asserted, an I2C reading

operation of the interrupt status registers clears the

interrupt provided the interrupting condition is removed.

If the interrupting condition is still present, nIRQ stays

asserted and the interrupt status bit stays set. The

interrupt status registers are 0x00h, 0x01h, 0x03h,

0x04h, 0x05h, 0xA0h, 0xA6h, and 0xE5h.

The ICs specific CMI determines which GPIOx is used

for the nIRQ pin. nIRQ is an open-drain output and

should be pulled up to an appropriate supply voltage

with a 10kΩ or greater pull-up resistor.

nRESET

The ACT88320 provides a reset function to issue a

master reset to the system CPU/controller. nRESET is

immediately asserted low when either the VIN voltage

is above or below the UV or OV thresholds or any power

supply that is connected to the nRESET functionality

goes below its Power Good threshold. The IC’s specific

CMI configures which power supplies are connected to

the nRESET functionality. After startup, nRESET

de-asserts after a programmable delay time when VIN

and all connected power supply outputs are above their

respective UVLO thresholds. The reset delay time,

20ms to 100ms, is controlled by the I2C TRST_DLY

pin used for the reset functionality. The CMI also

programs which regulators outputs are monitored for

the reset functionality.

EXT_EN

The ACT88320 provides an external power supply

enable function, EXT_EN. EXT_EN is used to control

an external regulator or to provide a control signal to

other system components. It is used as part of the

sequencing profile and can be programmed to have

different input triggers as well as delay times. The IC’s

CMI programs the specific GPIOx pin used for the

EXT_EN functionality.

EXT_PG

The ACT88320 provides an external input trigger,

EXT_PG, for startup sequencing. EXT_PG can be used

as the startup trigger for one or of the power supplies.

EXT_EN and EXT_PG allow the IC to fully incorporate

one or more external power supplies into the startup

sequence. The IC’s CMI programs the specific GPIOx

pin used for the EXT_EN functionality.

Output Under/Over Voltage

The ACT88320 monitors the output voltages for under

voltage and over voltage conditions. If an output enters

an UV/OV fault condition, the IC shuts down all outputs

for 100ms and restarts with the programmed power up

sequence. If an output is in current limit, it is possible

that its voltage can drop below the UV threshold which

also shuts down all outputs. If that behavior is not

desired, mask the appropriate fault bit. Each output still

provides its real-time UV/OV fault status via its fault flag,

even if the fault is masked. Masking an OV/UV fault just

prevents the fault from being reported via the IRQ pin.

A UV/OV fault condition pulls the nRESET pin low. Note

that the IC’s specific CMI sets the defaults for which

regulators mask the UV and OV fault conditions.

Output Current Limit

The ACT88320 incorporates a three level overcurrent

protection scheme for the buck converters and a single

level scheme for the LDOs. For the buck converters, the

overcurrent current threshold refers to the peak switch

current. The first protection level is when a buck

converter’s peak switch current reaches 75% of the

Cycle-by-Cycle current limit threshold for greater than

16 switching cycles. Under this condition, the IC reports

the fault via the appropriate fault flag bit. If the fault is

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