ACT88320 datasheet(29/57 Pages) QORVO

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Data Sheet Rev. E, November 2019 | Subject to change without notice

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ACT88320

Advanced PMU with Inrush Control and Bypass Switch

BUCK1 BYPASS MODE

General Description

Buck1 is configurable as a bypass switch for systems

with a 3.3V bus voltage. The bypass switch provides full

sequencing capability by allowing the 3.3V bus to be

used as the input to the other supplies and still be

properly sequenced to the downstream load. In bypass

mode, the Buck1 P-ch FET acts as a switch and the

N-ch FET is disabled. The bypass switch turns on the

3.3V rail with the programmed delay and softstart time.

In bypass mode, the ACT88320 Buck 1 I2C registers are

reconfigured to the following.

ILIM bit is the output of the PMOS Current

Detection circuit. In an overcurrent condition,

ILIM triggers the nIRQ output. ILIM is latched

until read via I2C. ILIM can be masked with the

ILIM_FLTMSK register.

The UV register bit is reconfigured to the output

of the PMOS Current Shutdown circuit. This is

set to 5.6A typical. If the bypass switch current

exceeds 5.6A, it limits the current which triggers

an under voltage fault condition and moves the

into

the

OVUV

FAULT

state.

This

immediately shuts down all regulators including

the bypass switch. The system restarts in

100mS, following the programmed startup

sequencing. This fault can be masked with I2C

bit UV_FLTMASK. This fault is latched in the

UV_REG I2C bit.

OV is disabled. There is no overvoltage detec-

tion circuitry on the output of the bypass switch.

LDO CONVERTERS

General Description

The ACT88320 contains two fully integrated, 200mA,

low dropout linear regulators (LDO). LDOs have been

optimized to achieve low dropout and high PSRR.

The LDOs require only two small external components

(Cin, Cout) for operation. They ship with default output

voltages that can be modified via the I2C interface for

systems that require advanced power management

functions.

Soft-Start

Each LDO contains a softstart circuit that limits the rate

of change of the output voltage, minimizing input inrush

current and ensuring that the outputs power up

monotonically. This circuitry is effective any time the

LDO is enabled, as well as after responding to a short

circuit or other fault condition. Each LDO’s softstart time

is fixed to 275us.

Output Voltage Setting

The LDOs regulate to the voltage defined by their I2C

registers LDO1_VSET and LDO2_VSET. The LDOs do

not have a second VSET register like the buck

converters. The LDOs can be configured with two

different output voltage range settings. I2C register bit

VREF_CTRL controls the two settings. This bit is factory

set and is not user configurable.

VREF_CTRL = 0

VREF_CTRL = 1

Vref (V)

0.8

0.6

Vout

Range (V)

0.8 – 3.9875

0.6 – 2.991

Vout Step

Size (mV)

12.5

9.375

The following equation determines the LDO output

voltages when VREF_CTRL = 0.

VLDOx = 0.8V + LDOx_VSET * 0.0125V

The following equation determines the LDO output

voltages when VREF_CTRL = 1.

VLDOx = 0.6V + LDOx_VSET * 0.009375V

Active Semi recommends that the LDO’s output voltage

be kept within +/- 25% of the default output voltage to

maintain accuracy. Voltage changes larger than +/- 25%

may require different factory trim settings (new CMI) to

maintain accuracy.

Enable / Disable Control

During normal operation, each LDO may be enabled or

disabled via the I2C interface by writing to that

regulator's ON bit. Note that disabling an LDO that is

used as an input trigger to another regulator may or may

not disable the other regulators following it, depending

on the specific CMI settings. Each LDO has a load

discharge function designed to quickly pull the output

voltage to ground when the LDO is disabled. The circuit

connects an internal resistor (50ohm) from the output to

AGND when the LDO is disabled.

POK and Output Fault Interrupt

Each LDO features a power-OK status bit, POK, which

can be read by the system microprocessor via the

I2C interface. If an output voltage is lower than the

POK threshold, typically 11% below the programmed

regulation voltage, that regulator’s POK bit will be 0.

If an LDO's nFLTMSK[ ] bit is set to 1, the ACT88320

will interrupt the processor if that LDO’s output voltage

falls below the power-OK threshold. In this case, nIRQ

asserts low and remains asserted until either the LDO

is turned off or goes back into regulation, and the POK

[ ] bit has been read via I2C.

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