ACT88320 datasheet(25/57 Pages) QORVO

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Data Sheet Rev. E, November 2019 | Subject to change without notice

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ACT88320

Advanced PMU with Inrush Control and Bypass Switch

Pin Descriptions

Many of the ACT88320 input and output pins are

configurable via CMI configurations. The following

descriptions are refer to basic pin functions and

capabilities. Refer to the CMI Options section in the

back of the datasheet for specific pin functionality for

each CMI.

VIN

VIN pins are the dedicated input power to the buck

converters. Buck1 uses pins 17 and 18. Buck2 uses

pins 23 and 24. Buck 3 uses pins 1 and 2. Each buck

converter must be bypassed directly to PGND on the

top PCB layer with a 10uF capacitor.

AVIN

AVIN is the input power to the LDOs. It also powers

the IC’s analog circuitry. AVIN must be bypassed

directly to AGND on the top PCB layer with a 1uF

ceramic capacitor.

OVGATE

This pin drives the gate of an external N-ch FET.

OVGATE slowly turns on the FET to provide softstart

when power is applied. It quickly turns off the FET in an

overvoltage condition. Connect to PGND if the input

overvoltage FET is not used.

OVSNS, OVSNS_M

These are the positive and negative input current sense

pins. They should be kelvin connected to the input

current sense resistor. OVSNS is also the input voltage

sense pin. Connect to PGND if the input overvoltage

FET is not used.

VIO

This is the bias supply input to the IC’s digital circuitry.

It powers the GPIO pins. VIO is typically connected to

the VIN pins, but can be powered from a different

voltage rail if desired. VIO should be bypassed to PGND

with a 1uF ceramic capacitor.

PWREN

PWREN is a digital input that helps determine if the IC

operates in POWER ON mode or DPSLP mode. Refer

to the DPSLP State section for details. Refer to the EC

table to ensure that the PWREN input voltage meets the

IC’s logic level requirements.

PWREN is referenced to the AVIN pin, and is 5.5V

tolerant meaning that PWREN can go to 5.5V even if

AVIN is less than 5.5V. PWREN has a 10us bidirectional

filter to prevent unwanted triggering from noise.

GPIOx

The ACT88320 has four GPIO pins. Each GPIO is

programmed for a specific function by the IC’s CMI. The

available functions are input triggers for sequencing

(EXT_PG), output triggers for sequencing (EXT_EN),

nRESET, nIRQ, DVS, voltage select pins for the voltage

regulators, LED drivers, and GPIO.

GPIO1 (pin 13). GPIO1 can be programmed for any of

the above functions except the LED drivers. It can be

programmed for both open-drain and push-pull.

GPIO2 (pin 14). GPIO2 is the same as GPIO1

GPIO3 (pin 12). GPIO3 can be programmed for all the

above functions including the LED drivers. It can be only

be programmed for open-drain outputs.

GPIO4 (pin 11). GPIO4 is the same as GPIO3

GPIOx pins can be programmed as an input or an

output. They are 5.5V tolerant meaning they can go to

5.5V even if VIO is less than 5.5V.

SCL, SDA

These are the I2C clock and data pins to the IC. They

have standard I2C functionality.

PGND

The PGND pins are the buck converter power ground

pins. They connect directly to the buck converters’ low

side FETs. Buck1 and Buck2 use pin 21. Buck3 uses

pins 7 and 8. All PGND pins must be connected directly

to the IC’s exposed pad under the IC.

SWx

SWx are the switch nodes for the buck converters. They

connect directly to the buck inductor on the top layer.

FB_Bx

These are the feedback pins for the buck regulators.

They should be kelvin connected to the buck output

capacitors.

LSG1

LSG1 is the load switch FET gate drive pin.

OUT_LDOx

These are the LDO output pins. Each LDO output must

be bypassed to AGND with a 1uF capacitor.

AGND

AGND is the ground pin for the IC’s analog circuitry and

LDOs. AGND must be connected to the IC’s exposed

pad. The connection between AGND and the exposed

pad should not have high currents flowing through it.

EXPOSED PAD

The exposed pad is the ICs ground reference. All

ground pins must connect to the exposed pad. It must

be soldered to the PCB.

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