ACT88320 datasheet(46/57 Pages) QORVO

46 / 57 page

Data Sheet Rev. E, November 2019 | Subject to change without notice

46 of 57

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ACT88320

Advanced PMU with Inrush Control and Bypass Switch

Hardware Configuration

Because the Marvell Dean 88SS1074 system level configuration does not use the inrush control circuitry, the design

connects OVSNS, OVSNS_M, and OVGATE to ground. The inrush circuitry can be used with the ACT88320QI105 by

connecting them per the datasheet guidelines.

Startup

Buck2

VIN

LDO2

EXT_EN

0.5ms

Buck1

CMI 105 Startup

nRESET

20ms

0.5ms

1ms

Buck3

I2C Address

The ACT88320 7-bit I2C address is 0x25h. Use address 0x4Ah when writing and 0x4Bh when reading.

GPIO1 (pin 13) - nRESET

GPIO1 is configured as an open drain nRESET. nRESET goes open drain 20ms after LDO2 goes into regulation.

GPIO2 (pin 14) – EXT_EN

GPIO2 is configured as an open drain EXT_EN. EXT_EN goes high immediately after Buck2 goes into regulation.

EXT_EN can be used to sequence on an external supply.

GPIO3 (pin 12) – nIRQ

GPIO3 is configured as an open drain nIRQ.

GPIO4 (pin 11) – Buck3_VID

GPIO4 is configured as a VID input for Buck3. When Pin 11 = 1, Buck3 = 1.5V. When Pin 11 = 0, Buck3 = 1.35V. Pin 11

is intended to be hard wired on the PCB to provide the correct startup for different DDR memory types. In applications

not requiring a fixed DDR voltage, pin 11 can be changed at any time to change the Buck3 output voltage

SLEEP MODE

I2C default settings are SLEEP_MODE=0, SLEEP_EN=0, and SLEEP=0. Refer to the SLEEP State paragraph for details

on how to enter SLEEP Mode.

DPSLP MODE

I2C default settings are DPSLP_MODE=1, DPSLP_EN=0, and DPSLP=0. Refer to the DPSLP State paragraph for

details on how to enter DPSLP Mode.

ACT88320 Datasheet(PDF) 46 Page - Qorvo, Inc