ACT88320 datasheet(27/57 Pages) QORVO

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Data Sheet Rev. E, November 2019 | Subject to change without notice

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ACT88320

Advanced PMU with Inrush Control and Bypass Switch

Active Semi recommends that the buck converter’s

output voltage be kept within +/- 25% of the default

output voltage to maintain accuracy. Voltage changes

larger than +/- 25% may require different factory trim

settings (new CMI) to maintain accuracy.

DVS

Each buck converter supports Dynamic Voltage Scaling

(DVS). In normal operation for most CMI options, each

output regulates to the voltage programmed by its

VSET0 I2C register. During DVS, each output can be

programmed to regulate to its VSET1 voltage.

During the voltage transition between VSET0 to VSET1

and VSET1 to VSET0, the I2C bit FORCEPWM is set to

1 to force the buck converters into PWM mode. This

ensures that the output transition to the new voltage

level as quickly as possible. The outputs transition

between the two setpoints at a defined slew rate to

minimize inrush currents. Note that VSET0 must be set

higher than VSET1. Violating this requirement results in

an OV fault during DVS.

For fault free operation, the user must ensure output

load conditions plus the current required to charge the

output capacitance during a DVS rising voltage

condition does not exceed the current limit setting of the

regulator. As with any power supply, changing an output

voltage too fast can require a current higher than the

current limit setting. The user must ensure that the

voltage step, slew rate, and load current conditions do

not result in an instantaneous loading that results in a

current limit condition. See paragraph Dynamic Voltage

Scaling for options to enter and exit DVS.

Enable / Disable Control

During normal operation, each buck may be enabled or

disabled via the I2C interface by writing to that

regulator's ON bit. Note that disabling a regulator that is

used as an input trigger to another regulator may or may

not disable the other regulators following it, depending

on the specific CMI settings. Each buck converter has a

load discharge function designed to quickly pull the

output voltage to ground when the converter is disabled.

The circuit connects an internal resistor (4.4ohm for

Buck1 and 9.4ohms for Buck2/3) from the output to

PGND when the converter is disabled.

POK and Output Fault Interrupt

Each DC/DC features a power-OK status bit, POK,

which can be read by the system microprocessor via the

I2C interface. If an output voltage is lower than the POK

threshold,

typically

below

the

programmed

regulation voltage, that regulator’s POK bit will be 0.

If a DC/DC's nFLTMSK[ ] bit is set to 1, the ACT88320

will interrupt the processor if the DC/DC's output voltage

falls below the power-OK threshold. In this case, nIRQ

asserts low and remains asserted until either the

regulator is turned off or goes back into regulation, and

the POK [ ] bit has been read via I2C.

Optimizing Noise

Each buck converter contains several features available

via I2C to further optimize functionality. The top P-ch

FET’s turn-on timing can be shifted approximately

110ns from the master clock edge via the PHASE_DE-

LAY I2C bit. It can also be aligned to the rising or falling

clock edge via the PHASE I2C bit.

Minimum On-Time

The ACT88320 minimum on-time is approximately

125ns. If a buck converter’s calculated on-time is less

than 125ns with 2.25MHz operation, then the buck

converter must be operated at 1.125MHz. Active Semi

will generate the IC CMIs to ensure that the buck

converters do not run into the minimum on-time limita-

tions. The following equation calculates the on-time.

∗

Where Vout is the output voltage, VIN is the input

voltage, and FSW is the switching frequency.

Overcurrent and Short Circuit Protection

Each buck converter provides overcurrent and short

circuit protection with built in foldback protection.

Overcurrent protection is achieved with cycle-by-cycle

current limiting. The peak current threshold is set by the

ILIM_SET I2C bits.

If the peak current reaches 75% of the programmed

threshold for 16 consecutive switching cycles, the IC as-

serts nIRQ low and changes I2C bit ILIM_WARN = 1,

but continues to operate normally.

If the peak current reaches the programmed threshold,

the IC turns off the power FET for that switching cycle.

If the peak current reaches the threshold 16 consecutive

switching cycles, the IC asserts nIRQ low. This condi-

tion typically results in shutdown due to an UV condition

due to the shortened switching cycle.

A short circuit condition that results in the peak switch

current being 122.5% of ILIM_SET immediately shuts

down the supply and asserts nIRQ low if the fault bit is

not masked. The supply tries to restart in 14ms. If the

fault condition is not masked, the IC transitions to the

OVUV State, turns off all supplies, and restarts the sys-

tem in 100ms.

The buck converters also have built in current foldback

protection. After softstart is complete, if a short circuit or

overload condition causes the output to go out of regu-

lation for > 28us, the IC reduces the peak-to-peak cur-

rent limit to 1.5A. This reduces system level power dis-

sipation in short circuit or overload conditions. If the load

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